[Intel-gfx] [PATCH] drm/i915/icl, tgl: whitelist COMMON_SLICE_CHICKEN3 register

[Sagar Ghuge]

On 2/5/21 5:33 AM, Chris Wilson wrote:
> Quoting Sagar Ghuge (2021-02-05 00:33:10)
>> Adding this register to whitelist will allow UMD to toggle State Cache
>> Perf fix disable chicken bit.
>>
>>    "If this bit is enabled, RCC uses BTP+BTI as address tag in its state
>>    cache instead of BTI only"
>>
>> which will lead to dropping unnecessary render target flushes and stall
>> on scoreboard.
> 
> The rest of the register looks safe to expose, and it passes our sanity
> checks that the register is local to the context and should not affect
> others.
> 
>> Bspec: 11333
>> Bspec: 45829
>>
>> Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
> 
> Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
Thank you!

> The only missing piece of the puzzle that Joonas will require is a
> Link: to a reviewed userspace patch/MR to confirm the uABI.
Link to MR:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8766
> -Chris
>