[Intel-gfx] [PATCH 07/18] drm/i915/display13: Add Display13 power wells
Lucas De Marchi
lucas.demarchi at intel.com
Thu Feb 11 01:33:43 UTC 2021
On Thu, Jan 28, 2021 at 11:24:02AM -0800, Matt Roper wrote:
>Aside from the hardware-managed PG0, Display13 has power wells 1-2 and
>A-D. These power wells should be enabled/disabled according to the
>following dependency tree (enable top to bottom, disable bottom to top):
>
> PG0
> |
> --PG1--
> / \
> PGA --PG2--
> / | \
> PGB PGC PGD
>
>PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the
>bits that would have been PG 6-9 under the old scheme.
>
>PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same
>as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
>
>Bspec: 49233
>Bspec: 49503
>Bspec: 49504
>Bspec: 49505
>Bspec: 49296
>Bspec: 50090
>Bspec: 53920
>Cc: Anshuman Gupta <anshuman.gupta at intel.com>
>Cc: Imre Deak <imre.deak at intel.com>
>Cc: Anshuman Gupta <anshuman.gupta at intel.com>
>Cc: José Roberto de Souza <jose.souza at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> .../drm/i915/display/intel_display_power.c | 422 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_vdsc.c | 5 +-
> drivers/gpu/drm/i915/i915_reg.h | 10 +
> 3 files changed, 433 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index e17b1ca356c3..7dd12fe9137e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -1035,7 +1035,7 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> enum i915_power_well_id high_pg;
>
> /* Power wells at this level and above must be disabled for DC5 entry */
>- if (INTEL_GEN(dev_priv) >= 12)
>+ if (INTEL_GEN(dev_priv) >= 12 && !HAS_DISPLAY13(dev_priv))
> high_pg = ICL_DISP_PW_3;
> else
> high_pg = SKL_DISP_PW_2;
>@@ -3028,6 +3028,109 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_INIT))
>
>+/*
>+ * Display13 Power Domains
>+ *
>+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
>+ * dependency chain turns into a dependency tree on Display13:
>+ *
>+ * PG0
>+ * |
>+ * --PG1--
>+ * / \
>+ * PGA --PG2--
>+ * / | \
>+ * PGB PGC PGD
>+ *
>+ * Power wells must be enabled from top to bottom and disabled from bottom
>+ * to top. This allows pipes to be power gated independently.
>+ */
>+
>+#define D13_PW_D_POWER_DOMAINS ( \
>+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
>+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
>+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define D13_PW_C_POWER_DOMAINS ( \
>+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
>+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
>+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define D13_PW_B_POWER_DOMAINS ( \
>+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
>+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
>+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
when reviewing this in the spec I thought this was wrong... apparently transcoder_{b,c,d} power wells
are in PG2, but there is a clarification in bspec 49233:
"Transcoder B (registers reside in PG2, but access path goes through associated pipe)"
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define D13_PW_A_POWER_DOMAINS ( \
>+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
>+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define D13_PW_2_POWER_DOMAINS ( \
>+ D13_PW_B_POWER_DOMAINS | \
>+ D13_PW_C_POWER_DOMAINS | \
>+ D13_PW_D_POWER_DOMAINS | \
>+ BIT_ULL(POWER_DOMAIN_AUDIO) | \
>+ BIT_ULL(POWER_DOMAIN_VGA) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_G_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_H_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_PORT_DDI_I_LANES) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_G) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_H) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_I) | \
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+/*
>+ * D13 PW_1/PG_1 domains (under HW/DMC control):
>+ * - DBUF function (registers are in PW0)
>+ * - Transcoder A
>+ * - DDI_A and DDI_B
>+ *
>+ * D13 PW_0/PW_1 domains (under HW/DMC control):
>+ * - PCI
>+ * - Clocks except port PLL
>+ * - Shared functions:
>+ * * interrupts except pipe interrupts
>+ * * MBus except PIPE_MBUS_DBOX_CTL
>+ * * DBUF registers
>+ * - Central power except FBC
>+ * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
>+ */
>+
>+#define D13_DISPLAY_DC_OFF_POWER_DOMAINS ( \
>+ D13_PW_2_POWER_DOMAINS | \
>+ BIT_ULL(POWER_DOMAIN_MODESET) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
>+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
>+ BIT_ULL(POWER_DOMAIN_INIT))
>+
>+#define D13_AUX_D_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
>+#define D13_AUX_E_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
>+#define D13_AUX_F_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
>+#define D13_AUX_G_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_G)
>+#define D13_AUX_H_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_H)
>+#define D13_AUX_I_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_I)
>+#define D13_AUX_F_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
>+#define D13_AUX_G_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_G_TBT)
>+#define D13_AUX_H_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_H_TBT)
>+#define D13_AUX_I_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_I_TBT)
>+
>+#define D13_DDI_IO_F_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
>+#define D13_DDI_IO_G_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_G_IO)
>+#define D13_DDI_IO_H_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_H_IO)
>+#define D13_DDI_IO_I_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I_IO)
>+
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
>@@ -4532,6 +4635,319 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
> },
> };
>
>+static const struct i915_power_well_desc display13_power_wells[] = {
>+ {
>+ .name = "always-on",
>+ .always_on = true,
>+ .domains = POWER_DOMAIN_MASK,
>+ .ops = &i9xx_always_on_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ },
>+ {
>+ .name = "power well 1",
>+ /* Handled by the DMC firmware */
>+ .always_on = true,
>+ .domains = 0,
>+ .ops = &hsw_power_well_ops,
>+ .id = SKL_DISP_PW_1,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "DC off",
>+ .domains = D13_DISPLAY_DC_OFF_POWER_DOMAINS,
>+ .ops = &gen9_dc_off_power_well_ops,
>+ .id = SKL_DISP_DC_OFF,
>+ },
>+ {
>+ .name = "power well 2",
>+ .domains = D13_PW_2_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = SKL_DISP_PW_2,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
>+ .hsw.has_vga = true,
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "power well A",
>+ .domains = D13_PW_A_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_PW_A,
>+ .hsw.irq_pipe_mask = BIT(PIPE_A),
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "power well B",
>+ .domains = D13_PW_B_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_PW_B,
>+ .hsw.irq_pipe_mask = BIT(PIPE_B),
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "power well C",
>+ .domains = D13_PW_C_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_PW_C,
>+ .hsw.irq_pipe_mask = BIT(PIPE_C),
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "power well D",
>+ .domains = D13_PW_D_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &hsw_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_PW_D,
>+ .hsw.irq_pipe_mask = BIT(PIPE_D),
>+ .hsw.has_fuses = true,
>+ },
>+ },
>+ {
>+ .name = "DDI A IO",
>+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>+ }
>+ },
>+ {
>+ .name = "DDI B IO",
>+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>+ }
>+ },
>+ {
>+ .name = "DDI C IO",
>+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
>+ }
>+ },
>+ {
>+ .name = "DDI D IO",
>+ .domains = ICL_DDI_IO_D_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_DDI_D,
>+ }
>+ },
>+ {
>+ .name = "DDI E IO",
>+ .domains = ICL_DDI_IO_E_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_DDI_E,
>+ }
>+ },
>+ {
>+ .name = "DDI F TC1 IO",
>+ .domains = D13_DDI_IO_F_TC1_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>+ }
>+ },
>+ {
>+ .name = "DDI G TC2 IO",
>+ .domains = D13_DDI_IO_G_TC2_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>+ }
>+ },
>+ {
>+ .name = "DDI H TC3 IO",
>+ .domains = D13_DDI_IO_H_TC3_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
>+ }
>+ },
>+ {
>+ .name = "DDI I TC4 IO",
>+ .domains = D13_DDI_IO_I_TC4_POWER_DOMAINS,
>+ .ops = &hsw_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_ddi_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
>+ }
>+ },
>+ {
>+ .name = "AUX A",
>+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>+ },
>+ },
>+ {
>+ .name = "AUX B",
>+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>+ },
>+ },
>+ {
>+ .name = "AUX C",
>+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
>+ },
>+ },
>+ {
>+ .name = "AUX D",
>+ .domains = D13_AUX_D_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_AUX_D,
>+ },
>+ },
>+ {
>+ .name = "AUX E",
>+ .domains = D13_AUX_E_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = D13_PW_CTL_IDX_AUX_E,
>+ },
>+ },
>+ {
>+ .name = "AUX F TC1",
>+ .domains = D13_AUX_F_TC1_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>+ },
>+ },
>+ {
>+ .name = "AUX G TC2",
>+ .domains = D13_AUX_G_TC2_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>+ },
>+ },
>+ {
>+ .name = "AUX H TC3",
>+ .domains = D13_AUX_H_TC3_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
>+ },
>+ },
>+ {
>+ .name = "AUX I TC4",
>+ .domains = D13_AUX_I_TC4_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
>+ },
>+ },
>+ {
>+ .name = "AUX F TBT1",
>+ .domains = D13_AUX_F_TBT1_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
>+ .hsw.is_tc_tbt = true,
>+ },
>+ },
>+ {
>+ .name = "AUX G TBT2",
>+ .domains = D13_AUX_G_TBT2_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
>+ .hsw.is_tc_tbt = true,
>+ },
>+ },
>+ {
>+ .name = "AUX H TBT3",
>+ .domains = D13_AUX_H_TBT3_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
>+ .hsw.is_tc_tbt = true,
>+ },
>+ },
>+ {
>+ .name = "AUX I TBT4",
>+ .domains = D13_AUX_I_TBT4_IO_POWER_DOMAINS,
>+ .ops = &icl_aux_power_well_ops,
>+ .id = DISP_PW_ID_NONE,
>+ {
>+ .hsw.regs = &icl_aux_power_well_regs,
>+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
>+ .hsw.is_tc_tbt = true,
>+ },
>+ },
>+};
>+
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> int disable_power_well)
>@@ -4689,7 +5105,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> * The enabling order will be from lower to higher indexed wells,
> * the disabling order is reversed.
> */
>- if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
>+ if (HAS_DISPLAY13(dev_priv)) {
>+ err = set_power_wells(power_domains, display13_power_wells);
>+ } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
> err = set_power_wells_mask(power_domains, tgl_power_wells,
> BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
> } else if (IS_ROCKETLAKE(dev_priv)) {
>diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>index f58cc5700784..8d8be0a006c7 100644
>--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>@@ -473,13 +473,14 @@ intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
> *
> * - ICL eDP/DSI transcoder
>- * - Gen12+ (except RKL) pipe A
>+ * - Display12 (except RKL) pipe A
> *
> * For any other pipe, VDSC/joining uses the power well associated with
> * the pipe in use. Hence another reference on the pipe power domain
> * will suffice. (Except no VDSC/joining on ICL pipe A.)
> */
>- if (INTEL_GEN(i915) >= 12 && !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
>+ if (INTEL_GEN(i915) >= 12 && !HAS_DISPLAY13(i915) &&
>+ !IS_ROCKETLAKE(i915) && pipe == PIPE_A)
> return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
> else if (is_pipe_dsc(crtc_state))
> return POWER_DOMAIN_PIPE(pipe);
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 9dfa4d711d6f..ec7bda22f4f3 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -9619,6 +9619,12 @@ enum {
> #define ICL_PW_CTL_IDX_PW_2 1
> #define ICL_PW_CTL_IDX_PW_1 0
>
>+/* Display13 - power wells */
>+#define D13_PW_CTL_IDX_PW_D 8
>+#define D13_PW_CTL_IDX_PW_C 7
>+#define D13_PW_CTL_IDX_PW_B 6
>+#define D13_PW_CTL_IDX_PW_A 5
>+
> #define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
> #define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
> #define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
>@@ -9633,7 +9639,9 @@ enum {
> #define TGL_PW_CTL_IDX_AUX_TBT1 9
> #define ICL_PW_CTL_IDX_AUX_TBT1 8
> #define TGL_PW_CTL_IDX_AUX_TC6 8
>+#define D13_PW_CTL_IDX_AUX_E 8
> #define TGL_PW_CTL_IDX_AUX_TC5 7
>+#define D13_PW_CTL_IDX_AUX_D 7
> #define TGL_PW_CTL_IDX_AUX_TC4 6
> #define ICL_PW_CTL_IDX_AUX_F 5
> #define TGL_PW_CTL_IDX_AUX_TC3 5
>@@ -9648,7 +9656,9 @@ enum {
> #define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
> #define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
> #define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
>+#define D13_PW_CTL_IDX_DDI_E 8
> #define TGL_PW_CTL_IDX_DDI_TC6 8
>+#define D13_PW_CTL_IDX_DDI_D 7
> #define TGL_PW_CTL_IDX_DDI_TC5 7
> #define TGL_PW_CTL_IDX_DDI_TC4 6
> #define ICL_PW_CTL_IDX_DDI_F 5
>--
>2.25.4
>
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