[Intel-gfx] [PATCH 03/18] drm/i915/display13: Enhanced pipe underrun reporting

[Ville Syrjälä]

On Thu, Jan 28, 2021 at 11:23:58AM -0800, Matt Roper wrote:
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10fd0e3af2d4..a57593f7d7b1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6039,14 +6039,18 @@ enum {
>  #define   PIPECONF_DITHER_TYPE_ST2 (2 << 2)
>  #define   PIPECONF_DITHER_TYPE_TEMP (3 << 2)
>  #define _PIPEASTAT		0x70024
> +#define _PIPEASTAT_ICL		0x70058

PIPESTAT is a gmch thing. This is not that for sure.

>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL << 31)
>  #define   SPRITE1_FLIP_DONE_INT_EN_VLV		(1UL << 30)
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL << 29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL << 28)
> +#define   PIPE_STAT_SOFT_UNDERRUN_D13		(1UL << 28)
>  #define   PERF_COUNTER2_INTERRUPT_EN		(1UL << 27)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL << 27)
> +#define   PIPE_STAT_HARD_UNDERRUN_D13		(1UL << 27)
>  #define   PLANE_FLIP_DONE_INT_EN_VLV		(1UL << 26)
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL << 26)
> +#define   PIPE_STAT_PORT_UNDERRUN_D13		(1UL << 26)
>  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL << 25)
>  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL << 24)
>  #define   PIPE_DPST_EVENT_ENABLE		(1UL << 23)
> @@ -6111,6 +6115,7 @@ enum {
>  #define PIPEFRAME(pipe)		_MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
>  #define PIPEFRAMEPIXEL(pipe)	_MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
>  #define PIPESTAT(pipe)		_MMIO_PIPE2(pipe, _PIPEASTAT)
> +#define ICL_PIPESTAT(pipe)	_MMIO_PIPE2(pipe, _PIPEASTAT_ICL)
>  
>  #define  _PIPEAGCMAX           0x70010
>  #define  _PIPEBGCMAX           0x71010
> @@ -7789,6 +7794,8 @@ enum {
>  #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
>  #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
>  #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
> +#define  D13_PIPE_SOFT_UNDERRUN		(1 << 22)
> +#define  D13_PIPE_HARD_UNDERRUN		(1 << 21)
>  #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
>  #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
>  #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
> -- 
> 2.25.4
> 
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-- 
Ville Syrjälä
Intel