[Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

[Chiou, Cooper]

Hi upstream committee, 

Please consider to merge this patch which resolved VP8 hardware encoding GPU hang critical issue on Gen9 sku and there is no any performance regression on this fix. Meanwhile it's critical for Chrome projects need your help to review to merge it. Thanks,

Best Regards,
Cooper

-----Original Message-----
From: Chiou, Cooper <cooper.chiou at intel.com> 
Sent: Thursday, September 17, 2020 2:08 AM
To: intel-gfx at lists.freedesktop.org
Cc: Chiou, Cooper <cooper.chiou at intel.com>; Ville Syrjälä <ville.syrjala at linux.intel.com>; Vivi, Rodrigo <rodrigo.vivi at intel.com>; Nikula, Jani <jani.nikula at intel.com>; Chris Wilson <chris at chris-wilson.co.uk>; Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>; Tseng, William <william.tseng at intel.com>; Lee, Shawn C <shawn.c.lee at intel.com>
Subject: [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku

Reference: HSD#1508045018

Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin at linux.intel.com>
Cc: William Tseng <william.tseng at intel.com>
Cc: Lee Shawn C <shawn.c.lee at intel.com>
Signed-off-by: Cooper Chiou <cooper.chiou at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5726cd0a37e0..53ea4359545b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -935,9 +935,13 @@ hsw_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	wa_masked_en(wal, HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);  }
 
+static void wa_init_mcr(struct drm_i915_private *i915, struct 
+i915_wa_list *wal);
+
 static void
 gen9_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)  {
+	wa_init_mcr(i915, wal);
+
 	/* WaDisableKillLogic:bxt,skl,kbl */
 	if (!IS_COFFEELAKE(i915) && !IS_COMETLAKE(i915))
 		wa_write_or(wal,
@@ -1040,7 +1044,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	unsigned int slice, subslice;
 	u32 l3_en, mcr, mcr_mask;
 
-	GEM_BUG_ON(INTEL_GEN(i915) < 10);
+	GEM_BUG_ON(INTEL_GEN(i915) < 9);
 
 	/*
 	 * WaProgramMgsrForL3BankSpecificMmioReads: cnl,icl @@ -1049,7 +1053,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 	 * by default, to make sure we correctly read certain registers
 	 * later on (in the range 0xB100 - 0xB3FF).
 	 *
-	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:cnl,icl
+	 * WaProgramMgsrForCorrectSliceSpecificMmioReads:gen9,cnl,icl
 	 * Before any MMIO read into slice/subslice specific registers, MCR
 	 * packet control register needs to be programmed to point to any
 	 * enabled s/ss pair. Otherwise, incorrect values will be returned.
--
2.28.0