[Intel-gfx] [PATCH v2] drm/i915/display: Allow PSR2 selective fetch to be enabled at run-time

[Mun, Gwan-gyeong]

On Tue, 2021-02-09 at 12:50 -0800, José Roberto de Souza wrote:
> Right now CI is blacklisting module reload, so we need to be able to
> enable PSR2 selective fetch in run time to test this feature before
> enable it by default.
> Changes in IGT will also be needed.
> 
> v2:
> - Fixed handling of I915_PSR_DEBUG_ENABLE_SEL_FETCH in
> intel_psr_debug_set()
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 1 +
>  drivers/gpu/drm/i915/display/intel_psr.c           | 8 +++++---
>  2 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ebaa9d0ed376..577f47aa6b3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1425,6 +1425,7 @@ struct intel_psr {
>  #define I915_PSR_DEBUG_DISABLE         0x01
>  #define I915_PSR_DEBUG_ENABLE          0x02
>  #define I915_PSR_DEBUG_FORCE_PSR1      0x03
> +#define I915_PSR_DEBUG_ENABLE_SEL_FETCH        0x4
>  #define I915_PSR_DEBUG_IRQ             0x10
>  
>         u32 debug;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index bf214d0e2dec..43e9e362382b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -684,7 +684,8 @@ static bool
> intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>         struct intel_plane *plane;
>         int i;
>  
> -       if (!dev_priv->params.enable_psr2_sel_fetch) {
> +       if (!dev_priv->params.enable_psr2_sel_fetch &&
> +           intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
>                 drm_dbg_kms(&dev_priv->drm,
>                             "PSR2 sel fetch not enabled, disabled by
> parameter\n");
>                 return false;
> @@ -1448,7 +1449,8 @@ void intel_psr_update(struct intel_dp
> *intel_dp,
>         enable = crtc_state->has_psr;
>         psr2_enable = crtc_state->has_psr2;
>  
> -       if (enable == psr->enabled && psr2_enable == psr-
> >psr2_enabled) {
> +       if (enable == psr->enabled && psr2_enable == psr-
> >psr2_enabled &&
> +           crtc_state->enable_psr2_sel_fetch == psr-
> >psr2_sel_fetch_enabled) {
>                 /* Force a PSR exit when enabling CRC to avoid CRC
> timeouts */
>                 if (crtc_state->crc_enabled && psr->enabled)
>                         psr_force_hw_tracking_exit(intel_dp);
> @@ -1637,7 +1639,7 @@ int intel_psr_debug_set(struct intel_dp
> *intel_dp, u64 val)
>         int ret;
>  
>         if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) ||
> -           mode > I915_PSR_DEBUG_FORCE_PSR1) {
> +           mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
>                 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask
> %llx\n", val);
>                 return -EINVAL;
>         }

Looks good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>