[Intel-gfx] [PATCH v2] drm/i915/display: Do not allow DC3CO if PSR SF is enabled

[Souza, Jose]

On Mon, 2021-02-22 at 21:05 +0200, Gwan-gyeong Mun wrote:
> Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism
> has an issue with using of Selective Fecth and PSR2 manual tracking.
> And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking,
> Selective Fetch will be enabled by default on that platforms.
> Therefore if the system enables PSR Selective Fetch / PSR manual tracking,
> it does not allow DC3CO dc state, in that case.
> 
> When this DC3CO exit issue is addressed while PSR Selective Fetch is
> enabled, this restriction should be removed.
> 
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Anshuman Gupta <anshuman.gupta at intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7c6e561f86c1..7370de97e599 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -654,6 +654,14 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u32 exit_scanlines;
>  
> 
> 
> 
> +	/*
> +	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
> +	 * TODO: when the issue is addressed, this restriction should be removed.
> +	 */
> +	if (dev_priv->params.enable_psr2_sel_fetch ||
> +	    intel_dp->psr.debug == I915_PSR_DEBUG_ENABLE_SEL_FETCH)
> +		return;

crtc_state->enable_psr2_sel_fetch is a much better alternative.


> +
>  	if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
>  		return;
>  
> 
> 
>