[Intel-gfx] [PATCH] drm/i915: Verify dma_addr in gen8_ggtt_pte_encode

[Piorkowski, Piotr]

From: Piotr Piórkowski <piotr.piorkowski at intel.com>

Until now, the gen8_ggtt_pte_encode function, responsible for the preparation
of GGTT PTE, has not verified in any way whether the address given as the
parameter is correct.
By adding a GGTT address mask, we can easily verify that dma_addr will not fit
in the PTE field.
While around, cleanup a place where we hold all GEN12 GGTT PTE masks,
and the addition of the PTE description.

Bspec: 45015

Signed-off-by: Piotr Piórkowski <piotr.piorkowski at intel.com>
Cc: Matthew Auld <matthew.auld at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Michal Winiarski <michal.winiarski at intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt.c |  2 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h  | 13 ++++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index b0b8ded834f0..52b2428da431 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -193,6 +193,8 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
 {
 	gen8_pte_t pte = addr | _PAGE_PRESENT;
 
+	GEM_BUG_ON(addr & ~GEN12_GGTT_PTE_ADDR_MASK);
+
 	if (flags & PTE_LM)
 		pte |= GEN12_GGTT_PTE_LM;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 24b5808df16d..c82bbe307668 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -87,7 +87,18 @@ typedef u64 gen8_pte_t;
 
 #define GEN12_PPGTT_PTE_LM	BIT_ULL(11)
 
-#define GEN12_GGTT_PTE_LM	BIT_ULL(1)
+/*
+ *  DOC: GEN12 GGTT Table Entry format
+ *
+ * +----------+---------+---------+--------------+---------+
+ * |    63:46 |   45:12 |    11:2 |            1 |       0 |
+ * +==========+=========+=========+==============+=========+
+ * |  Ignored | Address | Ignored | Local Memory | Present |
+ * +----------+---------+---------+--------------+---------+
+ */
+
+#define GEN12_GGTT_PTE_LM		BIT_ULL(1)
+#define GEN12_GGTT_PTE_ADDR_MASK	GENMASK_ULL(45, 12)
 
 /*
  * Cacheability Control is a 4-bit value. The low three bits are stored in bits
-- 
2.25.1