[Intel-gfx] [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail

[Abodunrin, Akeem G]

> -----Original Message-----
> From: Chris Wilson <chris at chris-wilson.co.uk>
> Sent: Saturday, January 09, 2021 7:50 AM
> To: intel-gfx at lists.freedesktop.org
> Cc: Chris Wilson <chris at chris-wilson.co.uk>; Mika Kuoppala
> <mika.kuoppala at linux.intel.com>; Kumar Valsan, Prathap
> <prathap.kumar.valsan at intel.com>; Abodunrin, Akeem G
> <akeem.g.abodunrin at intel.com>; Bloomfield, Jon
> <jon.bloomfield at intel.com>
> Subject: [PATCH 2/3] drm/i915/gt: Restore clear-residual mitigations for
> Ivybridge, Baytrail
> 
> The mitigation is required for all gen7 platforms, now that it does not cause
> GPU hangs, restore it for Ivybridge and Baytrail.
> 
> Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
> Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
> Cc: Bloomfield Jon <jon.bloomfield at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 4ea741f488a8..72d4722441bf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -1326,7 +1326,7 @@ int intel_ring_submission_setup(struct
> intel_engine_cs *engine)
> 
>  	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
> 
> -	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
> +	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
>  		err = gen7_ctx_switch_bb_init(engine);
>  		if (err)
>  			goto err_ring_unpin;
> --
> 2.20.1

I tried hard to remember why checking for HSW platform specifically in this case, since mitigation is applicable to all gen 7 (including 7.5) platforms - but couldn't recall why, and see no reason in the code doing it that way - so the changes make sense...

Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>