[Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on GT

[Abodunrin, Akeem G]

> -----Original Message-----
> From: Chris Wilson <chris at chris-wilson.co.uk>
> Sent: Monday, January 11, 2021 1:03 PM
> To: Abodunrin, Akeem G <akeem.g.abodunrin at intel.com>; intel-
> gfx at lists.freedesktop.org
> Cc: stable@ <vger.kernel.org stable at vger.kernel.org>; Randy Wright
> <rwright at hpe.com>
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Limit VFE threads based on
> GT
> 
> Quoting Abodunrin, Akeem G (2021-01-11 20:25:34)
> > >  static void
> > >  batch_get_defaults(struct drm_i915_private *i915, struct batch_vals *bv)
> {
> > >       if (IS_HASWELL(i915)) {
> > > -             bv->max_primitives = 280;
> > > -             bv->max_urb_entries = MAX_URB_ENTRIES;
> > > +             switch (INTEL_INFO(i915)->gt) {
> > > +             default:
> > > +             case 1:
> > > +                     bv->max_threads = 70;
> > > +                     break;
> > > +             case 2:
> > > +                     bv->max_threads = 140;
> > > +                     break;
> > > +             case 3:
> > > +                     bv->max_threads = 280;
> > > +                     break;
> > > +             }
> > >               bv->surface_height = 16 * 16;
> > >               bv->surface_width = 32 * 2 * 16;
> > >       } else {
> > > -             bv->max_primitives = 128;
> > > -             bv->max_urb_entries = MAX_URB_ENTRIES / 2;
> > > +             switch (INTEL_INFO(i915)->gt) {
> > > +             default:
> > > +             case 1: /* including vlv */
> > > +                     bv->max_threads = 36;
> > > +                     break;
> > > +             case 2:
> > > +                     bv->max_threads = 128;
> > > +                     break;
> > > +             }
> > Do we really need to hardcode max number of threads per gt/platform?
> Why not calculating the number of active threads from the no_of_slices *
> 1024? - Also, is "64" not the minimum number of threads supported?
> 
> ivb,byt,hsw each has different numbers of threads per subslice, and each gt
> has a different number of subslice/slice (and not a simple doubling of
> subslice/slice from 1 -> 2 -> 3, although the total is!).
> 
> It's a choice between encoding a tuple for (num_threads, num_subslices,
> num_slices) or the combined value.
> 
> The goal is to run a shader in each HW thread to clear the thread-local
> registers, and only one shader in each.
> -Chris

Okay, let's go with simplified solution to achieve our goal here, instead of complex calculation...

Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>