[Intel-gfx] [CI 2/3] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail

Chris Wilson chris at chris-wilson.co.uk
Mon Jan 11 22:52:19 UTC 2021

The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.

Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan at intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
Cc: Bloomfield Jon <jon.bloomfield at intel.com>
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 1c6d421f6fe5..724d56c9583d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1324,7 +1324,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine)
 	GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
-	if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
+	if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
 		err = gen7_ctx_switch_bb_init(engine);
 		if (err)
 			goto err_ring_unpin;

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