[Intel-gfx] [PATCH 08/22] drm/i915/adl_s: Configure DPLL for ADL-S

[Matt Roper]

On Fri, Dec 04, 2020 at 05:08:30PM -0800, Aditya Swarup wrote:
> Add changes for configuring DPLL for ADL-S
> - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
> - Extend CNL macro to choose DPLL_ENABLE
>   for ADL-S.
> - Select CFGCR0 and CFGCR1 for ADL-S plls.
> 
> On BSpec: 53720 PLL arrangement dig for adls:
> DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
> DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)

53720 shows DPLL's 0/1/2/3 in the diagram but the registers are named as
DPLL 0/1/3/4 (no #2).  I don't see anywhere on 53720 that it explicitly
gives the mapping you mention here, but on page 53723 I see a note:

        Due to current BSpec filtering limitations, the DPLL4_CRCFG0/1
        (164294h/164298h) are used to control the DPLL2.

Assuming that's correct, the patch below has the registers for the last
two DPLL's swapped.

...
> +
> +#define _ADLS_DPLL3_CFGCR1		0x1642C4
> +#define _ADLS_DPLL4_CFGCR1		0x164298
> +#define ADLS_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> +						   _TGL_DPLL1_CFGCR1, \
> +						   _ADLS_DPLL3_CFGCR1, \
> +						   _ADLS_DPLL4_CFGCR1)

I.e., this should be 

        #define ADLS_DPLL_CFGCR1(pll)	_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
                                                        _TGL_DPLL1_CFGCR1, \
                                                        _ADLS_DPLL4_CFGCR1, \
                                                        _ADLS_DPLL3_CFGCR1)

Given the strange spec naming, I think this calls for a comment in the
code as well to clarify that yes, we really do want 4 before 3 and that
there's no 2.


Matt

> +
>  #define _DKL_PHY1_BASE			0x168000
>  #define _DKL_PHY2_BASE			0x169000
>  #define _DKL_PHY3_BASE			0x16A000
> -- 
> 2.27.0
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795