[Intel-gfx] [PATCH] drm/i915/gt: Clear CACHE_MODE prior to clearing residuals

Chris Wilson chris at chris-wilson.co.uk
Sat Jan 16 22:31:17 UTC 2021

Since we do a bare context switch with no restore, the clear residual
kernel runs on dirty state, and we must be careful to avoid executing
bad state from context registers inherited from a malicious client.

Fixes: 008ead6ef8f5 ("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail")
Fixes: 09aa9e45863e ("drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail")
Testcase: igt/gem_ctx_isolation # ivb,vlv
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin at intel.com>
 drivers/gpu/drm/i915/gt/gen7_renderclear.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
index 56bdcdaa9a88..7d015416e4c4 100644
--- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c
+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c
@@ -390,6 +390,13 @@ static void emit_batch(struct i915_vma * const vma,
+	batch_add(&cmds, MI_LOAD_REGISTER_IMM(1));
+	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0));
+	batch_add(&cmds, 0xffff0000);
+	batch_add(&cmds, MI_LOAD_REGISTER_IMM(1));
+	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));
+	batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);
 	batch_add(&cmds, MI_NOOP);

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