[Intel-gfx] [PATCH 05/10] drm/i915/adl_s: Configure DPLL for ADL-S
Lucas De Marchi
lucas.demarchi at intel.com
Mon Jan 25 18:45:10 UTC 2021
On Mon, Jan 25, 2021 at 06:07:48AM -0800, Aditya Swarup wrote:
>Add changes for configuring DPLL for ADL-S
>- Reusing DG1 DPLL 2 & DPLL 3 for ADL-S
>- Extend CNL macro to choose DPLL_ENABLE
> for ADL-S.
>- Select CFGCR0 and CFGCR1 for ADL-S plls.
>
>On BSpec: 53720 PLL arrangement dig for adls:
>DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1)
>DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1)
>
>v2 (Lucas): add missing update_ref_clks
>
>Bspec: 50288
>Bspec: 50289
>Bspec: 49443
>
>v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield
>for DPLL3_USED.(mdroper)
>
>Bspec: 53707
>
>v4: BSpec 53723 has been updated with note - DPLL2 is
>controlled by DPLL4 CFGCR 0/1.(mdroper)
>
>Cc: Jani Nikula <jani.nikula at intel.com>
>Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
>Cc: Imre Deak <imre.deak at intel.com>
>Cc: Matt Roper <matthew.d.roper at intel.com>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Aditya Swarup <aditya.swarup at intel.com>
>Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 38 +++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++-
> 2 files changed, 54 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>index f6ad257a260e..529b1d569af2 100644
>--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>@@ -3559,7 +3559,13 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>
> icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ dpll_mask =
>+ BIT(DPLL_ID_DG1_DPLL3) |
>+ BIT(DPLL_ID_DG1_DPLL2) |
>+ BIT(DPLL_ID_ICL_DPLL1) |
>+ BIT(DPLL_ID_ICL_DPLL0);
I think mixing the namespace when it's not just an extension to the
other platform, it's a bit confusing. Why not DPLL_ID_DG1_* or even
creating your own DPLL_ID_ADLS_*.
Anyway, this seems a minor thing to block the patch. The rest looks ok.
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
>+ } else if (IS_DG1(dev_priv)) {
> if (port == PORT_D || port == PORT_E) {
> dpll_mask =
> BIT(DPLL_ID_DG1_DPLL2) |
>@@ -3865,7 +3871,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> if (!(val & PLL_ENABLE))
> goto out;
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
>+ hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
>+ } else if (IS_DG1(dev_priv)) {
> hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
> hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
> } else if (IS_ROCKETLAKE(dev_priv)) {
>@@ -3921,7 +3930,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> const enum intel_dpll_id id = pll->info->id;
> i915_reg_t cfgcr0_reg, cfgcr1_reg;
>
>- if (IS_DG1(dev_priv)) {
>+ if (IS_ALDERLAKE_S(dev_priv)) {
>+ cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
>+ cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
>+ } else if (IS_DG1(dev_priv)) {
> cfgcr0_reg = DG1_DPLL_CFGCR0(id);
> cfgcr1_reg = DG1_DPLL_CFGCR1(id);
> } else if (IS_ROCKETLAKE(dev_priv)) {
>@@ -4384,6 +4396,22 @@ static const struct intel_dpll_mgr dg1_pll_mgr = {
> .dump_hw_state = icl_dump_hw_state,
> };
>
>+static const struct dpll_info adls_plls[] = {
>+ { "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
>+ { "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
>+ { "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
>+ { "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
>+ { },
>+};
>+
>+static const struct intel_dpll_mgr adls_pll_mgr = {
>+ .dpll_info = adls_plls,
>+ .get_dplls = icl_get_dplls,
>+ .put_dplls = icl_put_dplls,
>+ .update_ref_clks = icl_update_dpll_ref_clks,
>+ .dump_hw_state = icl_dump_hw_state,
>+};
>+
> /**
> * intel_shared_dpll_init - Initialize shared DPLLs
> * @dev: drm device
>@@ -4397,7 +4425,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
> const struct dpll_info *dpll_info;
> int i;
>
>- if (IS_DG1(dev_priv))
>+ if (IS_ALDERLAKE_S(dev_priv))
>+ dpll_mgr = &adls_pll_mgr;
>+ else if (IS_DG1(dev_priv))
> dpll_mgr = &dg1_pll_mgr;
> else if (IS_ROCKETLAKE(dev_priv))
> dpll_mgr = &rkl_pll_mgr;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 0fe499840b82..339532222d7c 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2930,7 +2930,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define MBUS_BBOX_CTL_S2 _MMIO(0x45044)
>
> #define HDPORT_STATE _MMIO(0x45050)
>-#define HDPORT_DPLL_USED_MASK REG_GENMASK(14, 12)
>+#define HDPORT_DPLL_USED_MASK REG_GENMASK(15, 12)
> #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
> #define HDPORT_ENABLED REG_BIT(0)
>
>@@ -10394,11 +10394,14 @@ enum skl_power_gate {
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> #define DPLL1_ENABLE 0x46014
>+#define _ADLS_DPLL2_ENABLE 0x46018
>+#define _ADLS_DPLL3_ENABLE 0x46030
> #define PLL_ENABLE (1 << 31)
> #define PLL_LOCK (1 << 30)
> #define PLL_POWER_ENABLE (1 << 27)
> #define PLL_POWER_STATE (1 << 26)
>-#define CNL_DPLL_ENABLE(pll) _MMIO_PLL(pll, DPLL0_ENABLE, DPLL1_ENABLE)
>+#define CNL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
>+ _ADLS_DPLL2_ENABLE, _ADLS_DPLL3_ENABLE)
>
> #define TBT_PLL_ENABLE _MMIO(0x46020)
>
>@@ -10644,6 +10647,21 @@ enum skl_power_gate {
> _DG1_DPLL2_CFGCR1, \
> _DG1_DPLL3_CFGCR1)
>
>+/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
>+#define _ADLS_DPLL3_CFGCR0 0x1642C0
>+#define _ADLS_DPLL4_CFGCR0 0x164294
>+#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>+ _TGL_DPLL1_CFGCR0, \
>+ _ADLS_DPLL4_CFGCR0, \
>+ _ADLS_DPLL3_CFGCR0)
>+
>+#define _ADLS_DPLL3_CFGCR1 0x1642C4
>+#define _ADLS_DPLL4_CFGCR1 0x164298
>+#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>+ _TGL_DPLL1_CFGCR1, \
>+ _ADLS_DPLL4_CFGCR1, \
>+ _ADLS_DPLL3_CFGCR1)
>+
> #define _DKL_PHY1_BASE 0x168000
> #define _DKL_PHY2_BASE 0x169000
> #define _DKL_PHY3_BASE 0x16A000
>--
>2.27.0
>
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