[Intel-gfx] [PATCH 3/9] drm/i915/adl_s: Add power wells

Aditya Swarup aditya.swarup at intel.com
Thu Jan 28 05:30:18 UTC 2021

From: Lucas De Marchi <lucas.demarchi at intel.com>

TGL power wells can be re-used for ADL-S with the exception of the fake
power well for TC_COLD, just like DG-1.

BSpec: 53597
Bspec: 49231

Cc: Imre Deak <imre.deak at intel.com>
Cc: Matt Roper <matthew.d.roper at intel.com>
Cc: Aditya Swarup <aditya.swarup at intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup at intel.com>
Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 708f0b7e0990..cccfd45a67cf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4689,7 +4689,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	 * The enabling order will be from lower to higher indexed wells,
 	 * the disabling order is reversed.
-	if (IS_DG1(dev_priv)) {
+	if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) {
 		err = set_power_wells_mask(power_domains, tgl_power_wells,
 	} else if (IS_ROCKETLAKE(dev_priv)) {

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