[Intel-gfx] [PATCH 1/1] drm/i915/dg1: Compute MEM Bandwidth using MCHBAR

[Souza, Jose]

On Wed, 2021-06-30 at 21:06 -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor at intel.com>
> 
> The PUNIT FW is currently returning 0 for all memory bandwidth
> parameters. Read the values directly from MCHBAR offsets 0x5918 and
> 0x4000(4).
> 
> v2 (Lucas): tidy up checking for ret slightly
> v3 (Lucas):
>   - Squash change to double the memory bandwidth based on
>     MCHBAR Gear_type
>   - Move ICL_GEAR_TYPE_MASK to the appropriate place and change prefix
>     to DG1
>   - Move register definitions to i915_reg.h
>   - Make the MCHBAR path permanent for DG1
>   - Convert to REG_BIT()/REG_GENMASK()
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Jani Saarinen <jani.saarinen at intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 41 ++++++++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h         | 12 ++++++++
>  2 files changed, 52 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index bfb398f0432e..c913c2151680 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -23,6 +23,41 @@ struct intel_qgv_info {
>  	u8 t_bl;
>  };
>  
> +static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
> +					  struct intel_qgv_point *sp,
> +					  int point)
> +{
> +	u32 dclk_ratio = 0, dclk_reference = 0;
> +	u32 val = 0;

Only one nitpick, the initializations above are not needed.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> +
> +	val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
> +	dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
> +	if (val & DG1_QCLK_REFERENCE)
> +		dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
> +	else
> +		dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
> +	sp->dclk = dclk_ratio * dclk_reference;
> +
> +	val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
> +	if (val & DG1_GEAR_TYPE)
> +		sp->dclk *= 2;
> +
> +	if (sp->dclk == 0)
> +		return -EINVAL;
> +
> +	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
> +	sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
> +	sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
> +
> +	val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
> +	sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
> +	sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
> +
> +	sp->t_rc = sp->t_rp + sp->t_ras;
> +
> +	return 0;
> +}
> +
>  static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  					 struct intel_qgv_point *sp,
>  					 int point)
> @@ -99,7 +134,11 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>  	for (i = 0; i < qi->num_points; i++) {
>  		struct intel_qgv_point *sp = &qi->points[i];
>  
> -		ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> +		if (IS_DG1(dev_priv))
> +			ret = dg1_mchbar_read_qgv_point_info(dev_priv, sp, i);
> +		else
> +			ret = icl_pcode_read_qgv_point_info(dev_priv, sp, i);
> +
>  		if (ret)
>  			return ret;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65c155b14189..182190da3036 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11063,6 +11063,7 @@ enum skl_power_gate {
>  #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
>  #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
>  #define  SKL_REQ_DATA_MASK			(0xF << 0)
> +#define  DG1_GEAR_TYPE				REG_BIT(16)
>  
>  #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
>  #define  SKL_DRAM_DDR_TYPE_MASK			(0x3 << 0)
> @@ -11098,6 +11099,17 @@ enum skl_power_gate {
>  #define  CNL_DRAM_RANK_3			(0x2 << 9)
>  #define  CNL_DRAM_RANK_4			(0x3 << 9)
>  
> +#define SA_PERF_STATUS_0_0_0_MCHBAR_PC		_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
> +#define  DG1_QCLK_RATIO_MASK			REG_GENMASK(9, 2)
> +#define  DG1_QCLK_REFERENCE			REG_BIT(10)
> +
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4000)
> +#define   DG1_DRAM_T_RDPRE_MASK			REG_GENMASK(16, 11)
> +#define   DG1_DRAM_T_RP_MASK			REG_GENMASK(6, 0)
> +#define MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x4004)
> +#define   DG1_DRAM_T_RCD_MASK			REG_GENMASK(15, 9)
> +#define   DG1_DRAM_T_RAS_MASK			REG_GENMASK(8, 1)
> +
>  /*
>   * Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
>   * since on HSW we can't write to it using intel_uncore_write.