[Intel-gfx] [PATCH 7/8] drm/i915/fbc: Implement Wa_16011863758 for icl+

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

There's some kind of weird corner cases in FBC which requires
FBC segments to be separated by at least one extra cacheline.
Make sure that is present.

TODO: the formula laid out in the spec seem to be semi-nonsense
so this is mostly my interpretation on what it is actually trying
to say. Need to wait for clarification from the hw folks to know
for sure.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2da5295092e7..daf2191dd3f6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -88,6 +88,16 @@ static unsigned int intel_fbc_cfb_stride(struct drm_i915_private *i915,
 {
 	unsigned int stride = _intel_fbc_cfb_stride(cache);
 
+	/*
+	 * Wa_16011863758: icl+
+	 * CFB segment stride needs at least one extra cacheline.
+	 * We make sure each line has an extra cacheline so that
+	 * the 4 line segment will have one regarless of the
+	 * compression limit we choose later.
+	 */
+	if (DISPLAY_VER(i915) >= 11)
+		stride = max(stride, cache->plane.src_w * 4 + 64u);
+
 	/*
 	 * At least some of the platforms require each 4 line segment to
 	 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
-- 
2.31.1