[Intel-gfx] [PATCH V3] drm/i915/adl_s: Fix dma_mask_size to 39 bit

[Matthew Auld]

On Thu, 8 Jul 2021 at 08:21, Tejas Upadhyay
<tejaskumarx.surendrakumar.upadhyay at intel.com> wrote:
>
> 46 bit addressing enables you to use 4 bits  to support some
> MKTME features, and 3 more bits for Optane support that uses
> a subset of MTKME for persistent memory.
>
> But GTT addressing sticking to 39 bit addressing, thus setting
> dma_mask_size to 39 fixes below tests :
> igt at i915_selftest@live at mman
> igt at kms_big_fb@linear-32bpp-rotate-0
> igt at gem_create@create-clear
> igt at gem_mmap_offset@clear
> igt at gem_mmap_gtt@cpuset-big-copy
>
> In a way solves Gitlab#3142
> https://gitlab.freedesktop.org/drm/intel/-/issues/3142, which had
> following errors :
> DMAR: DRHD: handling fault status reg 2
> DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr
> 7effff9000 [fault reason 05] PTE Write access is not set
>
> 0x7effff9000 is suspiciously exactly 39 bits, so it seems likely that
> the HW just ends up masking off those extra bits hence DMA errors.
>
> Changes since V2 :
>         - dim checkpatch error solved
> Changes since V1 :
>         - Added more details to commit message - Matthew Auld
>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay at intel.com>
> Acked-by: Matthew Auld <matthew.auld at intel.com>

Pushed to drm-intel-gt-next. Thanks for the patch.