[Intel-gfx] [PATCH v2 1/4] iommu/vt-d: Disable superpage for Geminilake igfx

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

While running "gem_exec_big --r single" from igt-gpu-tools on
Geminilake as soon as a 2M mapping is made I tend to get a DMAR
write fault. Strangely the faulting address is always a 4K page
and usually very far away from the 2M page that got mapped.
But if no 2M mappings get used I can't reproduce the fault.

I also tried to dump the PTE for the faulting address but it actually
looks correct to me (ie. definitely seems to have the write bit set):
 DMAR: DRHD: handling fault status reg 2
 DMAR: [DMA Write] Request device [00:02.0] PASID ffffffff fault addr 7fa8a78000 [fault reason 05] PTE Write access is not set
 DMAR: fault 7fa8a78000 (level=1) PTE = 149efc003

So not really sure what's going on and this might just be full on duct
tape, but it seems to work here. The machine has now survived a whole day
running that test whereas with superpage enabled it fails in less than
a minute usually.

Credit to Lu Baolu for the mechanism to disable superpage just
for the igfx iommu.

TODO: would be nice to use the macros from include/drm/i915_pciids.h,
      but can't do that with DECLARE_PCI_FIXUP_HEADER()

Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Lu Baolu <baolu.lu at linux.intel.com>
Cc: iommu at lists.linux-foundation.org
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/iommu/intel/iommu.c | 34 +++++++++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index b04bfb0d9409..08ba412053e3 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -365,6 +365,7 @@ static int intel_iommu_strict;
 static int intel_iommu_superpage = 1;
 static int iommu_identity_mapping;
 static int iommu_skip_te_disable;
+static int iommu_skip_igfx_superpage;
 
 #define IDENTMAP_GFX		2
 #define IDENTMAP_AZALIA		4
@@ -674,6 +675,27 @@ static bool domain_update_iommu_snooping(struct intel_iommu *skip)
 	return ret;
 }
 
+static bool domain_use_super_page(struct dmar_domain *domain)
+{
+	struct dmar_drhd_unit *drhd;
+	struct intel_iommu *iommu;
+	bool ret = true;
+
+	if (!intel_iommu_superpage)
+		return false;
+
+	rcu_read_lock();
+	for_each_active_iommu(iommu, drhd) {
+		if (drhd->gfx_dedicated && iommu_skip_igfx_superpage) {
+			ret = false;
+			break;
+		}
+	}
+	rcu_read_unlock();
+
+	return ret;
+}
+
 static int domain_update_iommu_superpage(struct dmar_domain *domain,
 					 struct intel_iommu *skip)
 {
@@ -681,7 +703,7 @@ static int domain_update_iommu_superpage(struct dmar_domain *domain,
 	struct intel_iommu *iommu;
 	int mask = 0x3;
 
-	if (!intel_iommu_superpage)
+	if (!domain_use_super_page(domain))
 		return 0;
 
 	/* set iommu_superpage to the smallest common denominator */
@@ -5653,6 +5675,16 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx);
 
+static void quirk_skip_igfx_superpage(struct pci_dev *dev)
+{
+	pci_info(dev, "Disabling IOMMU superpage for graphics on this chipset\n");
+	iommu_skip_igfx_superpage = 1;
+}
+
+/* Geminilake igfx appears to have issues with superpage */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3184, quirk_skip_igfx_superpage);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x3185, quirk_skip_igfx_superpage);
+
 static void quirk_iommu_rwbf(struct pci_dev *dev)
 {
 	if (risky_device(dev))
-- 
2.31.1