[Intel-gfx] [PATCH v2 33/50] drm/i915/dg2: Add cdclk table and reference clock

[Souza, Jose]

On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> Note that DG2 only has a single possible refclk frequency (38.4 MHz).
> 
> Bspec: 54034
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 24 ++++++++++++++++++++--
>  1 file changed, 22 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 71067a62264d..28ef6cbcb402 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1290,6 +1290,18 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
>  	{}
>  };
>  
> +static const struct intel_cdclk_vals dg2_cdclk_table[] = {
> +	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
> +	{ .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
> +	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
> +	{ .refclk = 38400, .cdclk = 192000, .divider = 3, .ratio = 15 },
> +	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
> +	{ .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
> +	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
> +	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
> +	{}

Two cdclk entries of this table was dropped in the latest version of spec(179200 and 192000(second)), removing those LGTM.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> +};
> +
>  static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
>  {
>  	const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
> @@ -1408,7 +1420,9 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
>  {
>  	u32 val, ratio;
>  
> -	if (DISPLAY_VER(dev_priv) >= 11)
> +	if (IS_DG2(dev_priv))
> +		cdclk_config->ref = 38400;
> +	else if (DISPLAY_VER(dev_priv) >= 11)
>  		icl_readout_refclk(dev_priv, cdclk_config);
>  	else if (IS_CANNONLAKE(dev_priv))
>  		cnl_readout_refclk(dev_priv, cdclk_config);
> @@ -2873,7 +2887,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_ALDERLAKE_P(dev_priv)) {
> +	if (IS_DG2(dev_priv)) {
> +		dev_priv->display.set_cdclk = bxt_set_cdclk;
> +		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk.table = dg2_cdclk_table;
> +	} else if (IS_ALDERLAKE_P(dev_priv)) {
>  		dev_priv->display.set_cdclk = bxt_set_cdclk;
>  		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
>  		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;