[Intel-gfx] [PATCH v2 17/50] drm/i915/xehpsdv: Add maximum sseu limits

[Yokoyama, Caz]

Reviewed-by: Caz Yokoyama <caz.yokoyama at intel.com>
-caz

On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> Due to the removal of legacy slices and the transition to a
> gslice/cslice/mslice/etc. design, we'll internally store all DSS
> under
> "slice0."
> 
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_sseu.c         | 5 ++++-
>  drivers/gpu/drm/i915/gt/intel_sseu.h         | 2 +-
>  drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c | 2 +-
>  3 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c
> b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index 5d1b7d06c96b..16c0552fcd1d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -145,7 +145,10 @@ static void gen12_sseu_info_init(struct intel_gt
> *gt)
>  	 * across the entire device. Then calculate out the DSS for
> each
>  	 * workload type within that software slice.
>  	 */
> -	intel_sseu_set_info(sseu, 1, 6, 16);
> +	if (IS_XEHPSDV(gt->i915))
> +		intel_sseu_set_info(sseu, 1, 32, 16);
> +	else
> +		intel_sseu_set_info(sseu, 1, 6, 16);
>  
>  	/*
>  	 * As mentioned above, Xe_HP does not have the concept of a
> slice.
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h
> b/drivers/gpu/drm/i915/gt/intel_sseu.h
> index 74487650b08f..204ea6709460 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.h
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h
> @@ -16,7 +16,7 @@ struct intel_gt;
>  struct drm_printer;
>  
>  #define GEN_MAX_SLICES		(6) /* CNL upper bound */
> -#define GEN_MAX_SUBSLICES	(8) /* ICL upper bound */
> +#define GEN_MAX_SUBSLICES	(32) /* XEHPSDV upper bound */
>  #define GEN_SSEU_STRIDE(max_entries) DIV_ROUND_UP(max_entries,
> BITS_PER_BYTE)
>  #define GEN_MAX_SUBSLICE_STRIDE GEN_SSEU_STRIDE(GEN_MAX_SUBSLICES)
>  #define GEN_MAX_EUS		(16) /* TGL upper bound */
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> index 714fe8495775..a424150b052e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c
> @@ -53,7 +53,7 @@ static void cherryview_sseu_device_status(struct
> intel_gt *gt,
>  static void gen10_sseu_device_status(struct intel_gt *gt,
>  				     struct sseu_dev_info *sseu)
>  {
> -#define SS_MAX 6
> +#define SS_MAX 8
>  	struct intel_uncore *uncore = gt->uncore;
>  	const struct intel_gt_info *info = &gt->info;
>  	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];