[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity

[Patchwork]

== Series Details ==

Series: series starting with [1/6] drm/i915/display/psr: Handle SU Y granularity
URL   : https://patchwork.freedesktop.org/series/91594/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
47efae2a069f drm/i915/display/psr: Handle SU Y granularity
a03bc073ba13 drm/i915/display/adl_p: Implement Wa_22012278275
-:66: WARNING:LONG_LINE: line length of 136 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:4600:
+#define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << TGL_EDP_PSR2_IO_BUFFER_WAKE_SHIFT)

-:74: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/i915_reg.h:4607:
+#define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << TGL_EDP_PSR2_FAST_WAKE_MIN_SHIFT)

total: 0 errors, 2 warnings, 0 checks, 52 lines checked
b08ac7934e09 drm/i915/display/adl_p: Implement Wa_16011168373
b84f76144d24 drm/i915/xelpd: Handle PSR2 SDP indication in the prior scanline
07e0f4c3c72b drm/i915/display/adl_p: Implement Wa_16011303918
4f4308c4b4f7 drm/i915/display/adl_p: Implement PSR changes
-:149: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/i915_reg.h:4660:
+#define PSR2_MAN_TRK_CTL(tran)					_MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A)

-:152: WARNING:LONG_LINE: line length of 127 exceeds 100 columns
#152: FILE: drivers/gpu/drm/i915/i915_reg.h:4663:
+#define  PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)		REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

-:162: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/i915_reg.h:4670:
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)

-:164: WARNING:LONG_LINE: line length of 130 exceeds 100 columns
#164: FILE: drivers/gpu/drm/i915/i915_reg.h:4672:
+#define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val)		REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val)

total: 0 errors, 4 warnings, 0 checks, 131 lines checked