[Intel-gfx] [PATCH V3] drm/i915/gen11: Disable cursor clock gating in HDR mode

[Ville Syrjälä]

On Fri, Jun 18, 2021 at 05:16:06PM +0530, Tejas Upadhyay wrote:
> Display underrun in HDR mode when cursor is enabled.
> RTL fix will be implemented CLKGATE_DIS_PSL_A bit 28-46520h.
> As per W/A 1604331009, Disable cursor clock gating in HDR mode.
> 
> Bspec : 33451
> 
> Changes since V2:
>         - Made it general gen11 WA
>         - Removed WA needed check
>         - Added cursor plane active check
>         - Once WA enable, software will not disable
> Changes since V1:
>         - Modified way CLKGATE_DIS_PSL bit 28 was modified
> 
> Cc: Souza Jose <jose.souza at intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  5 +++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6be1b31af07b..99b33455b945 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -383,6 +383,18 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
>  		               intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
>  }
>  
> +/* Wa_1604331009:icl,jsl,ehl */
> +static void
> +icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,

Pointless function arguments since they can be derived from the
crtc state.

> +		       const struct intel_crtc_state *crtc_state)
> +{
> +	if (crtc_state->active_planes & icl_hdr_plane_mask() &&

That doesn't mean HDR mode will be enabled. I would suggest extracting
the HDR mode stuff from bdw_set_pipemisc() into a small helper. Or
alternatively we could stick that into the crtc state even.

> +	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&

> +	    IS_GEN(dev_priv, 11))
> +		intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
> +			     CURSOR_GATING_DIS, CURSOR_GATING_DIS);
> +}

Where does it get turned back on?

> +
>  static bool
>  is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
>  {
> @@ -2939,6 +2951,9 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  	    needs_scalerclk_wa(new_crtc_state))
>  		icl_wa_scalerclkgating(dev_priv, pipe, true);
>  
> +	/* Wa_1604331009:icl,jsl,ehl */
> +	icl_wa_cursorclkgating(dev_priv, pipe, new_crtc_state);
> +
>  	/*
>  	 * Vblank time updates from the shadow to live plane control register
>  	 * are blocked if the memory self-refresh mode is active at that
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 955027799d1d..bbdd8429297d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4235,6 +4235,11 @@ enum {
>  #define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
>  #define   CGPSF_CLKGATE_DIS		(1 << 3)
>  
> +/*
> + * GEN11 clock gating regs
> + */
> +#define   CURSOR_GATING_DIS            BIT(28)
> +
>  /*
>   * Display engine regs
>   */
> -- 
> 2.31.1
> 
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-- 
Ville Syrjälä
Intel