[Intel-gfx] [PATCH 3/3] drm/i915/gtt: ignore min_page_size for paging structures

[Thomas Hellström]

On 6/23/21 3:38 PM, Matthew Auld wrote:
> On 23/06/2021 14:32, Thomas Hellström wrote:
>>
>> On 6/23/21 1:26 PM, Matthew Auld wrote:
>>> The min_page_size is only needed for pages inserted into the GTT, and
>>> for our paging structures we only need at most 4K bytes, so simply
>>> ignore the min_page_size restrictions here, otherwise we might see some
>>> severe overallocation on some devices.
>>>
>>> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
>>> Cc: Thomas Hellström <thomas.hellstrom at linux.intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c 
>>> b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> index 084ea65d59c0..61e8a8c25374 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>> @@ -16,7 +16,7 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct 
>>> i915_address_space *vm, int sz)
>>>   {
>>>       struct drm_i915_gem_object *obj;
>>> -    obj = i915_gem_object_create_lmem(vm->i915, sz, 0);
>>> +    obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
>>
>> So is this memory always required to be size aligned? or should it 
>> say sz, PAGE_SIZE?
>
> The scratch page also hits this path, which is another can of worms. 
> In terms of size it might need to be 64K(with proper physical 
> alignment), which is why we can't force 4K here, and instead need to 
> use the passed in size, where the returned page will have the same 
> alignment.

OK. Perhaps a comment to explain that?

Reviewed-by: Thomas Hellström <thomas.hellstrom at linux.intel.com>



>
>>
>> /Thomas
>>
>>