[Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

[Han, Zhen]

Dear Matt,

Yes, it needs the WA in TGL.  Not sure the ADL-S and RKL.
The issue is different from 1808121037.
Previously, it was not found which exact usage condition needs to disable RHWO in studying the Alibaba issue in SG1, so make this change in kernel. 
Should we move the " disable RHWO " to mesa default setting path? 

Thanks
Han Zhen
-----Original Message-----
From: Roper, Matthew D <matthew.d.roper at intel.com> 
Sent: Wednesday, March 3, 2021 11:37 AM
To: De Marchi, Lucas <lucas.demarchi at intel.com>
Cc: intel-gfx at lists.freedesktop.org; Liu, Jianjun <jianjun.liu at intel.com>; Han, Zhen <zhen.han at intel.com>
Subject: Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg1: WA GPU hang at RCC

On Tue, Mar 02, 2021 at 05:07:28PM -0800, Lucas De Marchi wrote:
> From: Zhen Han <zhen.han at intel.com>
> 
> GPU hangs at RCC. According to Wa_14012131227 we shouldn't have a hang 
> due to RHWO, but that is what we are observing, even without media 
> compressible render target. Feedback from HW engineers is to leave 
> RHWO disabled.

"14012131227" isn't the correct workaround number; that's a platform-specific identifier.  This should be referred to by its lineage number 22011054531 which is common across all affected platforms.
>From a quick scan, it looks like this isn't just a DG1 workaround, but also applies to at least TGL and ADL-S as well (and is pending for RKL).

I'm not sure we actually need this workaround in the kernel though.
We're already whitelisting this register for userspace to allow UMD's to apply workarounds to it directly (and UMD's are already doing their own programming of the register for Wa_1808121037).  So it may be best to leave the handling of this additional bit to them as well, especially if the desired handling doesn't quite match the officially documented workaround text.


Matt

> 
> Cc: Jianjun Liu <Jianjun.liu at intel.com>
> Cc: Chuansheng Liu <chuansheng.liu at intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada at intel.com>
> Signed-off-by: Zhen Han <zhen.han at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e678fa8d2ab9..5235fb70a69a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -739,6 +739,17 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	       FF_MODE2,
>  	       FF_MODE2_GS_TIMER_MASK,
>  	       FF_MODE2_GS_TIMER_224, 0);
> +
> +	/*
> +	 * Wa_14012131227
> +	 *
> +	 * Although the WA is described as causing corruption when using media
> +	 * compressible render target, leaving RHWO enabled is also causing
> +	 * gpu hang when using multiple concurrent render and media workloads.
> +	 * Disable it completely for now.
> +	 */
> +	wa_masked_en(wal, GEN7_COMMON_SLICE_CHICKEN1,
> +		     GEN9_RHWO_OPTIMIZATION_DISABLE);
>  }
>  
>  static void
> --
> 2.30.1
> 
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--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795