[Intel-gfx] [PATCH v2 3/3] drm/i915/display: Introduce new intel_psr_pause/resume function
Souza, Jose
jose.souza at intel.com
Sat Mar 6 16:32:38 UTC 2021
On Fri, 2021-03-05 at 22:04 +0200, Gwan-gyeong Mun wrote:
> This introduces the following function that can enable and disable psr
> without intel_crtc_state/drm_connector_state when intel_psr is already
> enabled with current intel_crtc_state and drm_connector_state information.
>
> - intel_psr_pause(): Pause current PSR. it deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR without intel_crtc_state and
> drm_connector_state. It activates paused psr state.
No users for this new APIs.
>
> v2: Add new _intel_psr_enable_locked() function for removing duplicated
> code. (Jose)
>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> drivers/gpu/drm/i915/display/intel_psr.c | 117 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 3 files changed, 100 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 45c6388fa605..e29ffa8e8051 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1455,6 +1455,7 @@ struct intel_psr {
> u16 su_x_granularity;
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> + bool paused;
Nit: Add this close to the other variables that tracks state. Right after bool enabled;
> struct delayed_work dc3co_work;
> struct drm_dp_vsc_sdp vsc;
> };
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index ce7ce82d6f1b..d90c0d769f26 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -957,27 +957,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
> IGNORE_PSR2_HW_TRACKING : 0);
> }
>
>
> -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state,
> - const struct drm_connector_state *conn_state)
> +static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
Change not related to the commig message, if you want to do this do in a separated patch.
> {
> - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> - struct intel_encoder *encoder = &dig_port->base;
> u32 val;
>
>
> - drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> -
> - intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> - intel_dp->psr.busy_frontbuffer_bits = 0;
> - intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> - intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> - /* DC5/DC6 requires at least 6 idle frames */
> - val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> - intel_dp->psr.dc3co_exit_delay = val;
> - intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> - intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> -
> /*
> * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> * will still keep the error set even after the reset done in the
> @@ -998,13 +982,26 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> intel_dp->psr.sink_not_reliable = true;
> drm_dbg_kms(&dev_priv->drm,
> "PSR interruption error set, not enabling PSR\n");
> - return;
> + return false;
> }
>
>
> + return true;
> +}
> +
> +static void _intel_psr_enable_locked(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + struct intel_encoder *encoder = &dig_port->base;
> + const struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(encoder->base.crtc->state);
> +
> + if (!psr_interrupt_error_check(intel_dp))
> + return;
> +
> drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> intel_dp->psr.psr2_enabled ? "2" : "1");
> - intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> - &intel_dp->psr.vsc);
> +
> intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
> intel_psr_enable_sink(intel_dp);
> intel_psr_enable_source(intel_dp);
> @@ -1013,6 +1010,32 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> intel_psr_activate(intel_dp);
> }
>
>
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + const struct drm_connector_state *conn_state)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u32 val;
> +
> + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
Move this warn_on to _intel_psr_enable_locked() so we can get this warning from resume() too.
> +
> + intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> + intel_dp->psr.busy_frontbuffer_bits = 0;
move busy_frontbuffer_bits to _intel_psr_enable_locked(), otherwise a bit set here before the pause could be kept set forever.
> + intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> + intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> + /* DC5/DC6 requires at least 6 idle frames */
> + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> + intel_dp->psr.dc3co_exit_delay = val;
> + intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> + intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> + intel_dp->psr.paused = false;
> +
> + intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> + &intel_dp->psr.vsc);
> +
> + _intel_psr_enable_locked(intel_dp);
> +}
> +
> /**
> * intel_psr_enable - Enable PSR
> * @intel_dp: Intel DP
> @@ -1150,6 +1173,60 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> }
>
>
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (!psr->enabled || psr->paused) {
Here only check for enabled, if it is paused enabled will be false.
> + mutex_unlock(&psr->lock);
> + return;
> + }
> +
> + intel_psr_disable_locked(intel_dp);
> + psr->paused = true;
> +
> + mutex_unlock(&psr->lock);
> +
> + cancel_work_sync(&psr->work);
> + cancel_delayed_work_sync(&psr->dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> + struct intel_psr *psr = &intel_dp->psr;
> +
> + if (!CAN_PSR(intel_dp))
> + return;
> +
> + mutex_lock(&psr->lock);
> +
> + if (psr->enabled || !psr->paused)
Only check for paused here, with the move of the warn_on asked above this will help us caught any scenario that have paused = true and enabled = true.
> + goto unlock;
> +
> + psr->paused = false;
> + _intel_psr_enable_locked(intel_dp);
> +
> +unlock:
> + mutex_unlock(&psr->lock);
> +}
> +
> static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0491a49ffd50..8cc5e78fb1d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -48,5 +48,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state,
> int color_plane);
> +void intel_psr_pause(struct intel_dp *intel_dp);
> +void intel_psr_resume(struct intel_dp *intel_dp);
No users.
>
>
> #endif /* __INTEL_PSR_H__ */
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