[Intel-gfx] [PATCH v2 00/23] Separate display version numbering and add XE_LPD (version 13)
Matt Roper
matthew.d.roper at intel.com
Thu Mar 11 15:33:52 UTC 2021
Upcoming platforms will be using an updated display architecture called
"XE_LPD." Despite the new name, XE_LPD is a pretty natural evolution
from the current design we've been using on TGL, RKL, DG1, and ADL-S.
This series provides the basic XE_LPD support that isn't tied to a
specific platform; any platforms incorporating the XE_LPD display IP
will have additional platform-specific display patches as well.
The arrival of this new display architecture coincides with a general
disaggregation of Intel GPUs' architecture version numbering for the
different component IP blocks. Going forward it isn't accurate to talk
about a platform using INTEL_GEN() anymore since the various IP blocks
(graphics, media, display) are moving to independent internal numbering
schemes that may have different granularity and move at different
cadences; the hardware teams have asked us to start tracking these
values separately for "graphics," "media," and "display" such that
anywhere that we need to do a numerical comparison on the architecture
version, we should need to use an IP-specific version number instead of
INTEL_GEN(). This series takes the first step along that path by
introducing a DISPLAY_VER(i915) macro that should be used in place of
INTEL_GEN() throughout the display code.
Although the next couple platforms we release won't support it yet, the
current expectation is that in the future the IP version will be
provided to software via MMIO registers inside each IP block so that we
won't need to do manual translation of PCI device ID -> platform -> IP
versions. Since those registers don't exist yet on current platforms
(or the next few we'll be revealing), for now we need to just hardcode
the IP versions into our device info structures.
Notes about display version numbering:
- We take advantage of the separate DISPLAY_VER() numbering to
eliminate the GLK special case in the display code --- GLK is
classified as "gen9" in i915, but technically has version 10 display
IP; we can now capture that directly in the platform definition and
eliminate some of the special case conditions elsewhere in the code.
- Similar simplification may be possible with VLV and CHV which are
based on display IP that's older than their INTEL_GEN value would
imply, but we'll leave those platforms be for now since the situation
there is a bit more complicated.
Note that there are a few general XE_LPD changes that aren't included
in this series and will be sent separately:
* Tiled surfaces need to be mapped into the GGTT in a special way
(using "Display Page Tables").
* Color management is programmed differently on Display13 (using a
logarithmic scheme). Since this relates to some new DRM property
uapi, we'll just leave color management mostly disabled in this
series and enable the new logarithmic color management later.
* Dither support -- Based on the feedback in v1 of the series, we're
probably going to need some uapi changes to handle dither properly in
general; that can happen in other threads.
v2:
- Incorporate the new "XE_LPD" preferred name from marketing
- Introduce DISPLAY_VER() and apply it to the entire i915 display/
subtree, as well as display-related code in i915_irq.c and
intel_pm.c.
- Rebase on latest drm-tip; some of the recent refactoring has moved
things to different files (e.g., the SKL+ universal plane code).
- Drop the dither patches since there's going to need to be some extra
discussion on proper uapi.
- Incorporate minor v1 review feedback from Lucas, Ville, Chris, and
Jani.
The previous version of this series is available here:
https://patchwork.freedesktop.org/series/86409/
Juha-Pekka Heikkilä (1):
drm/i915/xelpd: Support 128k plane stride
Manasi Navare (1):
drm/i915/xelpd: Add VRR guardband for VRR CTL
Matt Roper (15):
drm/i915/display: Convert gen5/gen6 tests to
IS_IRONLAKE/IS_SANDYBRIDGE
drm/i915: Add DISPLAY_VER()
drm/i915/display: Eliminate most usage of INTEL_GEN()
drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in
intel_pm.c
drm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriate in
i915_irq.c
drm/i915/display: Simplify GLK display version tests
drm/i915/xelpd: add XE_LPD display characteristics
drm/i915/xelpd: Handle proper AUX interrupt bits
drm/i915/xelpd: Enhanced pipe underrun reporting
drm/i915/xelpd: Define plane capabilities
drm/i915/xelpd: Handle new location of outputs D and E
drm/i915/xelpd: Add XE_LPD power wells
drm/i915/xelpd: Increase maximum watermark lines to 255
drm/i915/xelpd: Required bandwidth increases when VT-d is active
drm/i915/xelpd: Add Wa_14011503030
Uma Shankar (1):
drm/i915/xelpd: Handle LPSP for XE_LPD
Vandita Kulkarni (5):
drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
drm/i915/xelpd: Support DP1.4 compression BPPs
drm/i915: Get slice height before computing rc params
drm/i915/xelpd: Calculate VDSC RC parameters
drm/i915/xelpd: Add rc_qp_table for rcparams calculation
drivers/gpu/drm/i915/display/i9xx_plane.c | 56 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 14 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 7 +-
drivers/gpu/drm/i915/display/intel_audio.c | 18 +-
drivers/gpu/drm/i915/display/intel_bios.c | 22 +-
drivers/gpu/drm/i915/display/intel_bw.c | 13 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 66 +--
drivers/gpu/drm/i915/display/intel_color.c | 32 +-
.../gpu/drm/i915/display/intel_combo_phy.c | 8 +-
drivers/gpu/drm/i915/display/intel_crt.c | 12 +-
drivers/gpu/drm/i915/display/intel_crtc.c | 20 +-
drivers/gpu/drm/i915/display/intel_csr.c | 4 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 14 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 129 ++---
.../drm/i915/display/intel_ddi_buf_trans.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 265 +++++-----
drivers/gpu/drm/i915/display/intel_display.h | 8 +
.../drm/i915/display/intel_display_debugfs.c | 50 +-
.../drm/i915/display/intel_display_power.c | 480 +++++++++++++++++-
.../drm/i915/display/intel_display_power.h | 9 +
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 110 ++--
drivers/gpu/drm/i915/display/intel_dp_aux.c | 24 +-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 20 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 12 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 20 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 62 +--
drivers/gpu/drm/i915/display/intel_fdi.c | 6 +-
.../drm/i915/display/intel_fifo_underrun.c | 73 ++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 11 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 29 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 12 +-
drivers/gpu/drm/i915/display/intel_overlay.c | 12 +-
drivers/gpu/drm/i915/display/intel_panel.c | 18 +-
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 16 +-
drivers/gpu/drm/i915/display/intel_pps.c | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 47 +-
.../gpu/drm/i915/display/intel_qp_tables.c | 272 ++++++++++
.../gpu/drm/i915/display/intel_qp_tables.h | 34 ++
drivers/gpu/drm/i915/display/intel_sdvo.c | 8 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 16 +-
drivers/gpu/drm/i915/display/intel_tc.c | 8 +-
drivers/gpu/drm/i915/display/intel_tv.c | 8 +-
drivers/gpu/drm/i915/display/intel_vdsc.c | 128 ++++-
drivers/gpu/drm/i915/display/intel_vga.c | 4 +-
drivers/gpu/drm/i915/display/intel_vrr.c | 56 +-
drivers/gpu/drm/i915/display/skl_scaler.c | 8 +-
.../drm/i915/display/skl_universal_plane.c | 125 +++--
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_irq.c | 92 ++--
drivers/gpu/drm/i915/i915_pci.c | 13 +-
drivers/gpu/drm/i915/i915_reg.h | 47 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 147 +++---
57 files changed, 1888 insertions(+), 808 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h
--
2.25.4
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