[Intel-gfx] [PATCH 3/3] drm/i915: Rewrite CL/CTG L-shaped memory detection

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

Currently we try to detect a symmetric memory configurations
using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is
either only set on a very specific subset of machines or it
just does not exist (it's not mentioned in any public chipset
datasheets I've found). As it happens my CL/CTG machines never
set said bit, even if I populate the channels with identical
sticks.

So let's do the L-shaped memory detection the same way as the
desktop variants, ie. just look at the DRAM rank boundary
registers to see if both channels have an identical size.

With this my CL/CTG no longer claim L-shaped memory when I use
identical sticks. Also tested with non-matching sticks just to
make sure the L-shaped memory is still properly detected.

And for completeness let's update the debugfs code to dump
the correct set of registers on each platform.

Cc: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++-------
 drivers/gpu/drm/i915/i915_debugfs.c          | 16 ++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index afb39a88e57d..b4b3c71f1295 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -682,14 +682,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
 				swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
 				swizzle_y = I915_BIT_6_SWIZZLE_9_17;
 			}
-			break;
-		}
 
-		/* check for L-shaped memory aka modified enhanced addressing */
-		if (IS_GEN(i915, 4) &&
-		    !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
-			swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
-			swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			/* check for L-shaped memory aka modified enhanced addressing */
+			if (IS_GEN(i915, 4) &&
+			    intel_uncore_read16(uncore, C0DRB3_CL) !=
+			    intel_uncore_read16(uncore, C1DRB3_CL)) {
+				swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
+				swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
+			}
+			break;
 		}
 
 		if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7792a596dda1..0020e75a284a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -617,10 +617,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
 			   intel_uncore_read(uncore, DCC));
 		seq_printf(m, "DDC2 = 0x%08x\n",
 			   intel_uncore_read(uncore, DCC2));
-		seq_printf(m, "C0DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C0DRB3_BW));
-		seq_printf(m, "C1DRB3 = 0x%04x\n",
-			   intel_uncore_read16(uncore, C1DRB3_BW));
+
+		if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_BW));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_BW));
+		} else if (IS_GEN(dev_priv, 4)) {
+			seq_printf(m, "C0DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C0DRB3_CL));
+			seq_printf(m, "C1DRB3 = 0x%04x\n",
+				   intel_uncore_read16(uncore, C1DRB3_CL));
+		}
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
 			   intel_uncore_read(uncore, MAD_DIMM_C0));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 923a4d6c17d9..b0ffc2fedf49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3784,6 +3784,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define C0DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x206)
 #define C1DRB3_BW		_MMIO(MCHBAR_MIRROR_BASE + 0x606)
 
+/* 965gm,ctg DRAM channel configuration */
+#define C0DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1206)
+#define C1DRB3_CL		_MMIO(MCHBAR_MIRROR_BASE + 0x1306)
+
 /* snb MCH registers for reading the DRAM channel configuration */
 #define MAD_DIMM_C0			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
 #define MAD_DIMM_C1			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
-- 
2.26.2