[Intel-gfx] [PATCH] drm/i915: Avoid div-by-zero on gen2

[Chris Wilson]

Quoting Ville Syrjälä (2021-03-22 14:48:44)
> On Sun, Mar 21, 2021 at 04:30:32PM +0000, Chris Wilson wrote:
> > Quoting Chris Wilson (2021-03-21 16:28:07)
> > > Quoting Ville Syrjala (2021-03-21 16:10:38)
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > index ec28a6cde49b..0b2434e29d00 100644
> > > > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj,
> > > >         struct i915_ggtt_view view;
> > > >  
> > > >         if (i915_gem_object_is_tiled(obj))
> > > > -               chunk = roundup(chunk, tile_row_pages(obj));
> > > > +               chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
> > > 
> > > I was thinking the answer would be to align to the next page, and hey
> > > presto!
> > 
> > Wait, the tile row cannot be a single page. Something else is zero that
> > should not be.
> 
> How come? At least i915_tiling_ok() doesn't enforce any
> bigger lower bound.

This maybe the trap I'm falling into, thinking that all arch have at
least 4K tile rows. Some might say, "shouldn't the chunk be aligned to an
even tile row" as well, but I was never certain about that.
-Chris