[Intel-gfx] [PATCH v2 39/50] drm/i915/adl_p: Enable/disable loadgen sharing

[Imre Deak]

On Thu, Mar 25, 2021 at 11:07:09AM -0700, Matt Roper wrote:
> From: Mika Kahola <mika.kahola at intel.com>
> 
> Disable loadgen sharing for DP link rate 1.62 GHz and HDMI 5.94 GHz.
> For all other modes, we can enable loadgen sharing feature.
> 
> BSpec: 55359
> 
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Mika Kahola <mika.kahola at intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++++
>  drivers/gpu/drm/i915/i915_reg.h          | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1a5213447db1..d58f6d297a2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1460,6 +1460,14 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>  		val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
>  		val &= ~DKL_TX_DP20BITMODE;
>  		intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
> +
> +		if ((intel_crtc_has_dp_encoder(crtc_state) &&
> +		    crtc_state->port_clock == 162000) ||
> +		    (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> +		    crtc_state->port_clock == 594000))
> +			val |= DKL_TX_LOADGEN_SHARING_PMD_DISABLE;
> +		else
> +			val &= ~DKL_TX_LOADGEN_SHARING_PMD_DISABLE;

Setting this flags isn't needed any more by the spec (bspec 54956).

>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f25f68f3b2f4..393071cde6d4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10887,6 +10887,7 @@ enum skl_power_gate {
>  						     _DKL_TX_DPCNTL1)
>  
>  #define _DKL_TX_DPCNTL2				0x2C8
> +#define  DKL_TX_LOADGEN_SHARING_PMD_DISABLE            REG_BIT(12)
>  #define  DKL_TX_DP20BITMODE				(1 << 2)
>  #define DKL_TX_DPCNTL2(tc_port) _MMIO(_PORT(tc_port, \
>  						     _DKL_PHY1_BASE, \
> -- 
> 2.25.4
> 
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