[Intel-gfx] ✓ Fi.CI.BAT: success for Alder Lake-P Support (rev2)

[Patchwork]

== Series Details ==

Series: Alder Lake-P Support (rev2)
URL   : https://patchwork.freedesktop.org/series/89899/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10060 -> Patchwork_20091
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20091/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20091:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt at runner@aborted:
    - {fi-tgl-1115g4}:    NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20091/fi-tgl-1115g4/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).



Participating hosts (42 -> 38)
------------------------------

  Missing    (4): fi-kbl-soraka fi-bdw-gvtdvm fi-ilk-m540 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10060 -> Patchwork_20091

  CI-20190529: 20190529
  CI_DRM_10060: ca1f02fd329bec1a62fc515647b1fd2ecc6b7aac @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6081: fdff4bba7abf9cb7c8ea21abf14e36d344ebb8c1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20091: 379e0be23f047890cdd58c4ca44f2ab9029eb00e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

379e0be23f04 drm/i915/perf: Enable OA formats for ADL_P
c6bebd2308a2 drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
6c629895ef1a drm/i915/display/adl_p: Implement Wa_22011320316
706e22d8d64c drm/i915/adl_p: Implement Wa_22011091694
873e70b36f89 drm/i915/adl_p: Add IPs stepping mapping
50a252b4a002 drm/i915/adl_p: Update memory bandwidth parameters
339f29d0da3f drm/i915/adlp: Add PIPE_MISC2 programming
2859e7a26f76 drm/i915/bigjoiner: atomic commit changes for uncompressed joiner
c919653d488b drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner
1f56c398ed97 drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner
8b77135caf2c drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
f1a2e79c34cc drm/i915/adl_p: Add PLL Support
0b872982349a drm/i915/adl_p: Enable/disable loadgen sharing
38f0185bbe0e drm/i915/adl_p: Define and use ADL-P specific DP translation tables
34b2e80ee8c8 drm/i915/display: Introduce new intel_psr_pause/resume function
bca93cbf5918 drm/i915/display: Add PSR interrupt error check function
e3d2f3d8e800 drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
37e0eb134827 drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
a3bd392378ed drm/i915/adl_p: Tx escape clock with DSI
23743ef20e3e drm/i915/adl_p: MBUS programming
075f6d078c7f drm/i915: Move intel_modeset_all_pipes()
17add1f707f3 drm/i915: Introduce MBUS relative dbuf offsets
c400a5672183 drm/i915/adl_p: Add ddb allocation support
de648c5cfcdd drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
4c9202704607 drm/i915/adl_p: Enable modular fia
6a77eb96eadb drm/i915/adl_p: Implement TC sequences
bcbfac5840a5 drm/i915/adl_p: Handle TC cold
64297fea6102 drm/i915/display/tc: Rename safe_mode functions ownership
0a98c7eb58a4 drm/i915/adl_p: Add cdclk support for ADL-P
5608185661ae drm/i915/adl_p: Setup ports/phys
2beede9590f0 drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
62c7114fb15a drm/i915/adl_p: Add dedicated SAGV watermarks
172c8c97b24c drm/i915/adl_p: Add PCH support
01726de55f6e drm/i915/xelpd: Provide port/phy mapping for vbt
399cb3269226 drm/i915/xelpd: Add VRR guardband for VRR CTL
f6216e9e9950 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
a62c87014d6e drm/i915/xelpd: Calculate VDSC RC parameters
1733e1391418 drm/i915: Get slice height before computing rc params
a84964ed0f9d drm/i915/xelpd: Support DP1.4 compression BPPs
70c3509ba166 drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
3a868413743b drm/i915/xelpd: Add Wa_14011503030
11ef5b059192 drm/i915/xelpd: Required bandwidth increases when VT-d is active
ec8e4ff3faf8 drm/i915/xelpd: Increase maximum watermark lines to 255
2737fb6d9b50 drm/i915/xelpd: Add XE_LPD power wells
abc805f00044 drm/i915/xelpd: Handle new location of outputs D and E
07183c19b8aa drm/i915/xelpd: Define plane capabilities
3ecdad37cbcd drm/i915/xelpd: Enhanced pipe underrun reporting
a5348dda9410 drm/i915/xelpd: Handle proper AUX interrupt bits

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20091/index.html
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