[Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement Wa_22011091694

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces at lists.freedesktop.org> On Behalf Of Matt
> Roper
> Sent: Saturday, May 8, 2021 5:28 AM
> To: intel-gfx at lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH v3 45/48] drm/i915/adl_p: Implement
> Wa_22011091694
> 
> From: José Roberto de Souza <jose.souza at intel.com>
> 
> Adding a new hook to ADL-P just to avoid another platform check in
> gen12lp_init_clock_gating() but also open to it.
> 
> BSpec: 54369
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Mika Kahola <mika.kahola at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h |  3 +++  drivers/gpu/drm/i915/intel_pm.c
> | 12 +++++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 4c356fa9055f..6fd126b64727
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4185,6 +4185,9 @@ enum {
>  #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
>  #define   BXT_GMBUS_GATING_DIS		(1 << 14)
> 
> +#define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
> +#define   DPCE_GATING_DIS		REG_BIT(17)
> +
>  #define _CLKGATE_DIS_PSL_A		0x46520
>  #define _CLKGATE_DIS_PSL_B		0x46524
>  #define _CLKGATE_DIS_PSL_C		0x46528
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 36da17e1aa3c..013a5aef4c29
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7370,6 +7370,14 @@ static void gen12lp_init_clock_gating(struct
> drm_i915_private *dev_priv)
>  				 CLKREQ_POLICY_MEM_UP_OVRD, 0);
>  }
> 
> +static void adlp_init_clock_gating(struct drm_i915_private *dev_priv) {
> +	gen12lp_init_clock_gating(dev_priv);
> +
> +	/* Wa_22011091694:adlp */
> +	intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0,
> DPCE_GATING_DIS); }
> +
>  static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)  {
>  	gen12lp_init_clock_gating(dev_priv);
> @@ -7847,7 +7855,9 @@ static void nop_init_clock_gating(struct
> drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)  {
> -	if (IS_DG1(dev_priv))
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		dev_priv->display.init_clock_gating = adlp_init_clock_gating;
> +	else if (IS_DG1(dev_priv))
>  		dev_priv->display.init_clock_gating = dg1_init_clock_gating;
>  	else if (IS_GEN(dev_priv, 12))
>  		dev_priv->display.init_clock_gating =
> gen12lp_init_clock_gating;
> --
> 2.25.4
> 
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