[Intel-gfx] [CI 02/19] drm/i915/xelpd: Increase maximum watermark lines to 255

[Matt Roper]

XE_LPD continues to use the same "skylake-style" watermark
programming as other recent platforms.  The only change to the watermark
calculations compared to Display12 is that XE_LPD now allows a
maximum of 255 lines vs the old limit of 31.

Due to the larger possible lines value, the corresponding bits
representing the value in PLANE_WM are also extended, so make sure we
read/write enough bits.  Let's also take this opportunity to switch over
to the REG_FIELD notation.

Bspec: 49325
Bspec: 50419
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Cc: Anshuman Gupta <anshuman.gupta at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +--
 drivers/gpu/drm/i915/intel_pm.c | 15 +++++++++++----
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 871d839dfcb8..04072c7e9efa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6435,8 +6435,7 @@ enum {
 #define _CUR_WM_TRANS_B_0	0x71168
 #define   PLANE_WM_EN		(1 << 31)
 #define   PLANE_WM_IGNORE_LINES	(1 << 30)
-#define   PLANE_WM_LINES_SHIFT	14
-#define   PLANE_WM_LINES_MASK	0x1f
+#define   PLANE_WM_LINES_MASK	REG_GENMASK(21, 14)
 #define   PLANE_WM_BLOCKS_MASK	0x7ff /* skl+: 10 bits, icl+ 11 bits */
 
 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 00a5fe424c5a..86a78cbb60fc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5185,6 +5185,14 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
 	return level > 0;
 }
 
+static int skl_wm_max_lines(struct drm_i915_private *dev_priv)
+{
+	if (DISPLAY_VER(dev_priv) >= 13)
+		return 255;
+	else
+		return 31;
+}
+
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
 				 unsigned int latency,
@@ -5289,7 +5297,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 	if (!skl_wm_has_lines(dev_priv, level))
 		lines = 0;
 
-	if (lines > 31) {
+	if (lines > skl_wm_max_lines(dev_priv)) {
 		/* reject it */
 		result->min_ddb_alloc = U16_MAX;
 		return;
@@ -5585,7 +5593,7 @@ static void skl_write_wm_level(struct drm_i915_private *dev_priv,
 	if (level->ignore_lines)
 		val |= PLANE_WM_IGNORE_LINES;
 	val |= level->blocks;
-	val |= level->lines << PLANE_WM_LINES_SHIFT;
+	val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines);
 
 	intel_de_write_fw(dev_priv, reg, val);
 }
@@ -6193,8 +6201,7 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
 	level->enable = val & PLANE_WM_EN;
 	level->ignore_lines = val & PLANE_WM_IGNORE_LINES;
 	level->blocks = val & PLANE_WM_BLOCKS_MASK;
-	level->lines = (val >> PLANE_WM_LINES_SHIFT) &
-		PLANE_WM_LINES_MASK;
+	level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
 }
 
 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
-- 
2.25.4