[Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel

[Clint Taylor]

On 5/24/21 2:48 PM, José Roberto de Souza wrote:
> Commit c457d9cf256e ("drm/i915: Make sure we have enough memory
> bandwidth on ICL") assumes that we always have a non-zero
> dram_info->channels and uses it as a divisor.
> We need num memory channels to be at least 1 for sane bw limits
> checking, even when PCode returns 0 or there is a error reading it, so
> lets force it to 1 in this case.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 3a1ba52266a7..bfb398f0432e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -162,7 +162,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
>   {
>   	struct intel_qgv_info qi = {};
>   	bool is_y_tile = true; /* assume y tile may be used */
> -	int num_channels = dev_priv->dram_info.num_channels;
> +	int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
>   	int deinterleave;
>   	int ipqdepth, ipqdepthpch;
>   	int dclk_max;

Reviewed-by: Clint Taylor <Clinton.A.Taylor at intel.com>

-Clint