[Intel-gfx] [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission

[Matthew Brost]

On Thu, May 06, 2021 at 12:13:20PM -0700, Matthew Brost wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> 
> In GuC submission mode the CS is owned by the GuC FW, so all CS status
> interrupts are handled by it. We only need the user interrupt as that
> signals request completion.
> 
> Since we're now starting the engines directly in GuC submission mode
> when selected, we can stop switching back and forth between the
> execlists and the GuC programming and select directly the correct
> interrupt mask.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Signed-off-by: Matthew Brost <matthew.brost at intel.com>

Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> Cc: John Harrison <john.c.harrison at intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c        | 18 ++++++-----
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 31 -------------------
>  2 files changed, 11 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index d29126c458ba..f88c10366e58 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -194,14 +194,18 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
>  
>  void gen11_gt_irq_postinstall(struct intel_gt *gt)
>  {
> -	const u32 irqs =
> -		GT_CS_MASTER_ERROR_INTERRUPT |
> -		GT_RENDER_USER_INTERRUPT |
> -		GT_CONTEXT_SWITCH_INTERRUPT |
> -		GT_WAIT_SEMAPHORE_INTERRUPT;
>  	struct intel_uncore *uncore = gt->uncore;
> -	const u32 dmask = irqs << 16 | irqs;
> -	const u32 smask = irqs << 16;
> +	u32 irqs = GT_RENDER_USER_INTERRUPT;
> +	u32 dmask;
> +	u32 smask;
> +
> +	if (!intel_uc_wants_guc_submission(&gt->uc))
> +		irqs |= GT_CS_MASTER_ERROR_INTERRUPT |
> +			GT_CONTEXT_SWITCH_INTERRUPT |
> +			GT_WAIT_SEMAPHORE_INTERRUPT;
> +
> +	dmask = irqs << 16 | irqs;
> +	smask = irqs << 16;
>  
>  	BUILD_BUG_ON(irqs & 0xffff0000);
>  
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 335719f17490..38cda5d599a6 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -432,32 +432,6 @@ void intel_guc_submission_fini(struct intel_guc *guc)
>  	}
>  }
>  
> -static void guc_interrupts_capture(struct intel_gt *gt)
> -{
> -	struct intel_uncore *uncore = gt->uncore;
> -	u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> -	u32 dmask = irqs << 16 | irqs;
> -
> -	GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> -
> -	/* Don't handle the ctx switch interrupt in GuC submission mode */
> -	intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, dmask, 0);
> -	intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask, 0);
> -}
> -
> -static void guc_interrupts_release(struct intel_gt *gt)
> -{
> -	struct intel_uncore *uncore = gt->uncore;
> -	u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT;
> -	u32 dmask = irqs << 16 | irqs;
> -
> -	GEM_BUG_ON(INTEL_GEN(gt->i915) < 11);
> -
> -	/* Handle ctx switch interrupts again */
> -	intel_uncore_rmw(uncore, GEN11_RENDER_COPY_INTR_ENABLE, 0, dmask);
> -	intel_uncore_rmw(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0, dmask);
> -}
> -
>  static int guc_context_alloc(struct intel_context *ce)
>  {
>  	return lrc_alloc(ce, ce->engine);
> @@ -722,9 +696,6 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
>  void intel_guc_submission_enable(struct intel_guc *guc)
>  {
>  	guc_stage_desc_init(guc);
> -
> -	/* Take over from manual control of ELSP (execlists) */
> -	guc_interrupts_capture(guc_to_gt(guc));
>  }
>  
>  void intel_guc_submission_disable(struct intel_guc *guc)
> @@ -735,8 +706,6 @@ void intel_guc_submission_disable(struct intel_guc *guc)
>  
>  	/* Note: By the time we're here, GuC may have already been reset */
>  
> -	guc_interrupts_release(gt);
> -
>  	guc_stage_desc_fini(guc);
>  }
>  
> -- 
> 2.28.0
>