[Intel-gfx] [PATCH v3 05/10] drm/i915: Prepare for multiple gts

[Andi Shyti]

Hi Tvrtko,

> > [...]
> > 
> > >   static int
> > >   intel_gt_tile_setup(struct intel_gt *gt, unsigned int id, phys_addr_t phys_addr)
> > 
> > we don't actually need 'id', it's gt->info.id. It's introduced in
> > patch 3 with the value '0' but it's not needed.
> 
> I have a suspicion code got munged up over endless rebases and refactors.
> 
> This patch is the one which introduces the id member to gt->info. But it is not setting it, even though I suspect the intent was for intel_gt_tile_setup to do that.
> 
> Instead gt->info.id is only set to a valid value in last patch of this series inside intel_gt_probe_all:
> 
> +		gt->i915 = i915;
> +		gt->name = gtdef->name;
> +		gt->type = gtdef->type;
> +		gt->info.engine_mask = gtdef->engine_mask;
> +		gt->info.id = i;
> +
> +		drm_dbg(&i915->drm, "Setting up %s %u\n", gt->name, gt->info.id);
> +		ret = intel_gt_tile_setup(gt, i, phys_addr + gtdef->mapping_base);
> 
> And intel_gt_tile_setup then calls __intel_gt_init_early which assigns gt->i915 yet again.
> 
> So I'd say there is probably space to bring this all into a more streamlined flow, even more than what you suggest below.

yes, I noticed them!

Patch 3, 5 and 10 are very much connected with each other: 3
prepares for one tile, 5 prepares for multitile and 10 does the
multitile. While in between other patches are doing other things.

On top of some cleanups we could also rearrange the patches with
some squashing and reordering to have them a bit more linear and
also easier to review.

Andi