[Intel-gfx] [PATCH 3/3] drm/i915/dg2: Program recommended HW settings

[Clint Taylor]

Reviewed-by: Clint Taylor <Clinton.A.Taylor at intel.com>

-Clint


On 11/2/21 3:25 PM, Matt Roper wrote:
> The bspec's performance guide suggests programming specific values into
> a few registers for optimal performance.  Although these aren't
> workarounds, it's easiest to handle them inside the GT workaround
> functions (which will also ensure that the values set here are properly
> melded with other bits in the same registers that _are_ set by
> workarounds).
>
> Bspec: 68331, 45395
>
> Cc: Matt Atwood <matthew.s.atwood at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Siddiqui Ayaz A <ayaz.siddiqui at intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++++++++++++-
>   drivers/gpu/drm/i915/i915_reg.h             |  9 +++++++
>   2 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 37fd541a9719..51591119da15 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -558,6 +558,22 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>   	wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
>   }
>   
> +/*
> + * These settings aren't actually workarounds, but general tuning settings that
> + * need to be programmed on dg2 platform.
> + */
> +static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> +				   struct i915_wa_list *wal)
> +{
> +	wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> +			 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> +	wa_add(wal,
> +	       FF_MODE2,
> +	       FF_MODE2_TDS_TIMER_MASK,
> +	       FF_MODE2_TDS_TIMER_128,
> +	       0, false);
> +}
> +
>   /*
>    * These settings aren't actually workarounds, but general tuning settings that
>    * need to be programmed on several platforms.
> @@ -647,7 +663,7 @@ static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
>   static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>   				     struct i915_wa_list *wal)
>   {
> -	gen12_ctx_gt_tuning_init(engine, wal);
> +	dg2_ctx_gt_tuning_init(engine, wal);
>   
>   	/* Wa_16011186671:dg2_g11 */
>   	if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
> @@ -1482,6 +1498,14 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>   
>   	/* Wa_14014830051:dg2 */
>   	wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> +
> +	/*
> +	 * The following are not actually "workarounds" but rather
> +	 * recommended tuning settings documented in the bspec's
> +	 * performance guide section.
> +	 */
> +	wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> +	wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
>   }
>   
>   static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ee39d6bd0f3c..ef3b5732faad 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -731,6 +731,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>   
>   #define GEN12_OA_TLB_INV_CR _MMIO(0xceec)
>   
> +#define GEN12_SQCM		_MMIO(0x8724)
> +#define   EN_32B_ACCESS		REG_BIT(30)
> +
>   /* Gen12 OAR unit */
>   #define GEN12_OAR_OACONTROL _MMIO(0x2960)
>   #define  GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1
> @@ -8506,6 +8509,12 @@ enum {
>   #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>   #define  GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
>   
> +#define GEN11_L3SQCREG5				_MMIO(0xb158)
> +#define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
> +
> +#define XEHP_L3SCQREG7				_MMIO(0xb188)
> +#define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
> +
>   /* GEN8 chicken */
>   #define HDC_CHICKEN0				_MMIO(0x7300)
>   #define ICL_HDC_MODE				_MMIO(0xE5F4)