[Intel-gfx] [PATCH] drm/i915/display/dsc: Clamp the max DSC input BPP to connector's max bpp

[Manasi Navare]

Pipe_bpp limits are decided by connectors max bpp as computed in
compute_sink_pipe_bpp() before computing link and DSC config.
Currently dsc_compute_config() sets the max input bpp only based
on DSC Input BPPs supported and max bpc requested for the connector
but does not clamp it based on connector's max bpp.
This patch fixes that.

Cc: Jani Nikula <jani.nikula at intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare at intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 45373c213d9e..82209d995969 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1400,6 +1400,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		return -EINVAL;
 
 	pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+	pipe_bpp = min(pipe_bpp, limits->max_bpp);
 
 	/* Min Input BPC for ICL+ is 8 */
 	if (pipe_bpp < 8 * 3) {
-- 
2.19.1