[Intel-gfx] [PATCH] drm/i915/vlv_dsi: Double pixelclock on read-back for dual-link panels

[Hans de Goede]

Hi,

On 10/25/21 10:17, Jani Nikula wrote:
> On Sun, 24 Oct 2021, Hans de Goede <hdegoede at redhat.com> wrote:
>> In intel_dsi_get_config() double the pclk returned by foo_dsi_get_pclk()
>> for dual-link panels. This fixes the following WARN triggering:
>>
>>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in pixel_rate (expected 235710, found 118056)
>>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.pipe_mode.crtc_clock (expected 235710, found 118056)
>>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in hw.adjusted_mode.crtc_clock (expected 235710, found 118056)
>>  i915 0000:00:02.0: [drm] *ERROR* [CRTC:51:pipe A] mismatch in port_clock (expected 235710, found 118056)
>>  ------------[ cut here ]------------
>>  pipe state doesn't match!
>>  WARNING: CPU: 3 PID: 136 at drivers/gpu/drm/i915/display/intel_display.c:9125 intel_display_finish_reset+0x1bd3/0x2050 [i915]
>>  ...
>>
>> This has been tested on a Xiaomi Mi Pad 2 (with CHT x5-Z8500 SoC) tablet,
>> with a 1536x2048 dual-link DSI panel.
>>
>> Note this fix was taken from icl_dsi.c which does the same in
>> its get_config().
>>
>> Cc: Tsuchiya Yuto <kitakar at gmail.com>
>> Signed-off-by: Hans de Goede <hdegoede at redhat.com>
> 
> Acked-by: Jani Nikula <jani.nikula at intel.com>

Thank you, I've pushed this to drm-intel-next now.

Regards,

Hans


> 
>> ---
>>  drivers/gpu/drm/i915/display/vlv_dsi.c | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> index 3e646a58b38a..2b7909bc52ff 100644
>> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>> @@ -1265,7 +1265,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>>  				 struct intel_crtc_state *pipe_config)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>>  	u32 pclk;
>> +
>>  	drm_dbg_kms(&dev_priv->drm, "\n");
>>  
>>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>> @@ -1277,6 +1279,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
>>  		pclk = vlv_dsi_get_pclk(encoder, pipe_config);
>>  	}
>>  
>> +	if (intel_dsi->dual_link)
>> +		pclk *= 2;
>> +
>>  	if (pclk) {
>>  		pipe_config->hw.adjusted_mode.crtc_clock = pclk;
>>  		pipe_config->port_clock = pclk;
>