[Intel-gfx] [RFC 4/7] drm/i915/guc: Add GuC's error state capture output structures.

[Teres Alexis, Alan Previn]

Good catch - i missed that. Will fix it. Thanks again.

...alan

On Wed, 2021-11-24 at 12:08 +0200, Jani Nikula wrote:
> On Mon, 22 Nov 2021, Alan Previn <alan.previn.teres.alexis at intel.com> wrote:
> > Add GuC's error capture output structures and definitions as how
> > they would appear in GuC log buffer's error capture subregion after
> > an error state capture G2H event notification.
> 
> If it's for decoding data, should they all have __packed?
> 
> > Signed-off-by: Alan Previn <alan.previn.teres.alexis at intel.com>
> > ---
> >  .../gpu/drm/i915/gt/uc/intel_guc_capture.h    | 35 +++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
> > index df420f0f49b3..b2454b6cd778 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
> > @@ -29,6 +29,41 @@ struct __guc_mmio_reg_descr_group {
> >  	struct __guc_mmio_reg_descr * ext;
> >  };
> >  
> > +struct intel_guc_capture_out_data_header {
> > +	u32 reserved1;
> > +	u32 info;
> > +		#define GUC_CAPTURE_DATAHDR_SRC_TYPE GENMASK(3, 0) /* as per enum guc_capture_type */
> > +		#define GUC_CAPTURE_DATAHDR_SRC_CLASS GENMASK(7, 4) /* as per GUC_MAX_ENGINE_CLASSES */
> > +		#define GUC_CAPTURE_DATAHDR_SRC_INSTANCE GENMASK(11, 8)
> > +	u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 */
> > +	u32 guc_ctx_id; /* if type-instance, context index of hung context, else set to ~0 */
> > +	u32 num_mmios;
> > +		#define GUC_CAPTURE_DATAHDR_NUM_MMIOS GENMASK(9, 0)
> > +};
> > +
> > +struct intel_guc_capture_out_data {
> > +	struct intel_guc_capture_out_data_header capture_header;
> > +	struct guc_mmio_reg capture_list[0];
> > +};
> > +
> > +enum guc_capture_group_types {
> > +	GUC_STATE_CAPTURE_GROUP_TYPE_FULL,
> > +	GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL,
> > +	GUC_STATE_CAPTURE_GROUP_TYPE_MAX,
> > +};
> > +
> > +struct intel_guc_capture_out_group_header {
> > +	u32 reserved1;
> > +	u32 info;
> > +		#define GUC_CAPTURE_GRPHDR_SRC_NUMCAPTURES GENMASK(7, 0)
> > +		#define GUC_CAPTURE_GRPHDR_SRC_CAPTURE_TYPE GENMASK(15, 8)
> > +};
> > +
> > +struct intel_guc_capture_out_group {
> > +	struct intel_guc_capture_out_group_header group_header;
> > +	struct intel_guc_capture_out_data group_lists[0];
> > +};
> > +
> >  struct intel_guc_state_capture {
> >  	struct __guc_mmio_reg_descr_group *reglists;
> >  	u16 num_instance_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center