[Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay

[kernel test robot]

Hi Animesh,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20211008]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a014-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a732b
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
        git checkout 474a8190321f2836a1fe989326736d19dc9a732b
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp at intel.com>

All warnings (new ones prefixed by >>):

>> drivers/gpu/drm/i915/display/intel_dp.c:2780:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
           if (vsc->revision != 0x5 || vsc->revision != 0x7)
               ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +2780 drivers/gpu/drm/i915/display/intel_dp.c

  2756	
  2757	static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
  2758					     struct dp_sdp *sdp, size_t size)
  2759	{
  2760		size_t length = sizeof(struct dp_sdp);
  2761	
  2762		if (size < length)
  2763			return -ENOSPC;
  2764	
  2765		memset(sdp, 0, size);
  2766	
  2767		/*
  2768		 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
  2769		 * VSC SDP Header Bytes
  2770		 */
  2771		sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
  2772		sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
  2773		sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
  2774		sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
  2775	
  2776		/*
  2777		 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
  2778		 * per DP 1.4a spec and DP 2.0 spec respectively.
  2779		 */
> 2780		if (vsc->revision != 0x5 || vsc->revision != 0x7)
  2781			goto out;
  2782	
  2783		/* VSC SDP Payload for DB16 through DB18 */
  2784		/* Pixel Encoding and Colorimetry Formats  */
  2785		sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
  2786		sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
  2787	
  2788		switch (vsc->bpc) {
  2789		case 6:
  2790			/* 6bpc: 0x0 */
  2791			break;
  2792		case 8:
  2793			sdp->db[17] = 0x1; /* DB17[3:0] */
  2794			break;
  2795		case 10:
  2796			sdp->db[17] = 0x2;
  2797			break;
  2798		case 12:
  2799			sdp->db[17] = 0x3;
  2800			break;
  2801		case 16:
  2802			sdp->db[17] = 0x4;
  2803			break;
  2804		default:
  2805			MISSING_CASE(vsc->bpc);
  2806			break;
  2807		}
  2808		/* Dynamic Range and Component Bit Depth */
  2809		if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
  2810			sdp->db[17] |= 0x80;  /* DB17[7] */
  2811	
  2812		/* Content Type */
  2813		sdp->db[18] = vsc->content_type & 0x7;
  2814	
  2815	out:
  2816		return length;
  2817	}
  2818	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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