[Intel-gfx] [PATCH 08/11] drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware

[Andi Shyti]

Hi Matt,

> > > -	dg1_master_intr_enable(uncore->regs);
> > > -	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);
> > > +	dg1_master_intr_enable(dev_priv->gt.uncore->regs);
> > > +	intel_uncore_posting_read(dev_priv->gt.uncore, DG1_MSTR_TILE_INTR);
> > 
> > I guess this should also go under a for_each_gt()
> 
> DG1_MSTR_TILE_INTR (0x190008) is the top-level, one-per-PCI device
> interrupt register; we always access it via tile0's MMIO .  So in this
> case we do want to do this outside the loop since it's not a per-tile
> operation.

yes of course... we are writing to the master interrupt.

> We could probably simplify the dev_priv->gt.uncore parameter to just
> dev_priv->uncore to make this more obvious.

... it would be a nitpick, but nice to have.

Reviewed-by: Andi Shyti <andi.shyti at linux.intel.com>

Thanks,
Andi