[Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Prepare for per-lane drive settings by querying the desired vswing
> level per-lane.
> 
> Note that the code only does two loops, with each one writing the
> levels for two TX lanes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4c400f0e7347..1874a2ca8f3b 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1163,7 +1163,6 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
> -	int level = intel_ddi_level(encoder, crtc_state, 0);
>  	const struct intel_ddi_buf_trans *trans;
>  	int n_entries, ln;
>  	u32 val;
> @@ -1188,12 +1187,18 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	/* Program MG_TX_SWINGCTRL with values from vswing table */
>  	for (ln = 0; ln < 2; ln++) {
> +		int level;
> +
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> +
>  		val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
>  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
>  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
>  			trans->entries[level].mg.cri_txdeemph_override_17_12);
>  		intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
>  
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
> +
>  		val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
>  		val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
>  		val |= CRI_TXDEEMPH_OVERRIDE_17_12(
> @@ -1203,6 +1208,10 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  
>  	/* Program MG_TX_DRVCTRL with values from vswing table */
>  	for (ln = 0; ln < 2; ln++) {
> +		int level;
> +
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
> +
>  		val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
>  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
>  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
> @@ -1213,6 +1222,8 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
>  			CRI_TXDEEMPH_OVERRIDE_EN;
>  		intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
>  
> +		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);

I believe our code style requires that we have spaces, so it should be (2 * ln + 1).

With the answers requested in the previous patch:

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>


> +
>  		val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
>  		val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
>  			 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);