[Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+

[Souza, Jose]

On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Now that the link buf_trans, link training, and the
> combo/mg/dkl/snps phy programming are all fixed up we can
> allow per-lane DP drive settings on icl+. Make it so.

Reviewed-by: José Roberto de Souza <jose.souza at intel.com>

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 1a943ae38a6b..279371237fe9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -301,7 +301,10 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
>  static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
>  				       enum drm_dp_phy dp_phy)
>  {
> -	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
> +	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> +	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
> +		DISPLAY_VER(i915) >= 11;
>  }
>  
>  static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,