[Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in mocs init

[Siddiqui, Ayaz A]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper at intel.com>
> Sent: Thursday, September 2, 2021 5:47 AM
> To: Siddiqui, Ayaz A <ayaz.siddiqui at intel.com>
> Cc: intel-gfx at lists.freedesktop.org; Telukuntla, Sreedhar
> <sreedhar.telukuntla at intel.com>
> Subject: Re: [Intel-gfx] [PATCH V3 7/8] drm/i915/gt: Initialize L3CC table in
> mocs init
> 
> On Mon, Aug 30, 2021 at 09:52:39PM +0530, Ayaz A Siddiqui wrote:
> > From: Sreedhar Telukuntla <sreedhar.telukuntla at intel.com>
> >
> > Initialize the L3CC table as part of mocs initalization to program
> > LNCFCMOCSx registers, so that the mocs settings are available for
> > selection for subsequent memory transactions in driver load path.


> >
> > Signed-off-by: Sreedhar Telukuntla <sreedhar.telukuntla at intel.com>
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com>
> > ---
> >  drivers/gpu/drm/i915/gt/intel_mocs.c | 13 ++++++++++---
> >  1 file changed, 10 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 577a78dfedf99..405374f1d8ed2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -717,10 +717,9 @@ static u32 l3cc_combine(u16 low, u16 high)
> >  	     0; \
> >  	     i++)
> >
> > -static void init_l3cc_table(struct intel_engine_cs *engine,
> > +static void init_l3cc_table(struct intel_uncore *uncore,
> >  			    const struct drm_i915_mocs_table *table)  {
> > -	struct intel_uncore *uncore = engine->uncore;
> >  	unsigned int i;
> >  	u32 l3cc;
> >
> > @@ -746,7 +745,7 @@ void intel_mocs_init_engine(struct intel_engine_cs
> *engine)
> >  		init_mocs_table(engine, &table);
> >
> >  	if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
> > -		init_l3cc_table(engine, &table);
> > +		init_l3cc_table(engine->uncore, &table);
> 
> Can you clarify in the commit message why we still need to re-call this in
> intel_mocs_init_engine() if we've already done it in intel_mocs_init()?  I'm
> assuming it's because we lose these register values on engine resets, so in
> the execlist path we need to make sure they get re-applied after the reset?
> 
> 
> Matt
Yes for platform like DG1/TGL we are loosing the MOCS programming during engine reset.
While on XEHP-SDV , Programming of L3CC are retain during engine reset also since
There is no Renderer engine in XEHP-SVD so MOCS will not be programmed, that why we need to add
This patch, We have not tested on stickiness DG2 yet, but I do not see any harm if we program it again
This patch will be required for XEHP-SVD.  If there are any other concern then we may ignore this patch
as of now and continue with other patches of series.  I'll modify commit message with   more information.
-Ayaz
 
 
> 
> >
> >  	aux = build_aux_regs(engine, &table);
> >  	apply_aux_regs_engine(engine, aux);
> > @@ -776,6 +775,14 @@ void intel_mocs_init(struct intel_gt *gt)
> >  	if (flags & HAS_GLOBAL_MOCS)
> >  		__init_mocs_table(gt->uncore, &table,
> global_mocs_offset());
> >  	set_mocs_index(gt, &table);
> > +
> > +	/*
> > +	 * Initialize the L3CC table as part of mocs initalization to make
> > +	 * sure the LNCFCMOCSx registers are programmed for the
> subsequent
> > +	 * memory transactions including guc transactions
> > +	 */
> > +	if (flags & HAS_RENDER_L3CC)
> > +		init_l3cc_table(gt->uncore, &table);
> >  }
> >
> >  #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation
> (916) 356-2795