[Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

Matt Roper matthew.d.roper at intel.com
Thu Sep 2 23:26:11 UTC 2021


On Thu, Sep 02, 2021 at 03:59:44PM -0700, Lucas De Marchi wrote:
> On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
> > Cache-control registers for Command Stream(CMD_CCTL) are used
> > to set catchability for memory writes and reads outputted by
> > Command Streamers on Gen12 onward platforms.
> > 
> > These registers need to point un-cached(UC) MOCS index.
> > 
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui at intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
> > 2 files changed, 43 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 94e1937f8d296..38c66765ff94c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> > 				   i915_mmio_reg_offset(RING_NOPID(base)));
> > }
> > 
> > +/*
> > + * engine_fake_wa_init(), a place holder to program the registers
> > + * which are not part of a workaround.
> > + * Adding programming of those register inside workaround will
> > + * allow utilizing wa framework to proper application and verification.
> > + */
> > +static void
> > +engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > +{
> > +	u8 mocs;
> > +
> > +	if (GRAPHICS_VER(engine->i915) >= 12) {
> 
> this is including TGL. Shouldn't TGL be the exception here?

Until now we haven't been programming CMD_CCTL, so it's basically been
pointing at entry 0.  On TGL/RKL, undefined entry 0 is treated as UC.
Now that we start setting CMD_CCTL here, it will switch to point at
entry 3, which is explicitly UC, so the behavior shouldn't change, but
the code should be more obvious.

The place where TGL/RKL need an exception is how to setup undefined
table entries (which may be used by userspace; we're not going to point
CMD_CCTL or BLIT_CCTL at any of those now).  In general those undefined
entries should be treated as L3, but for ABI reasons we need to keep
them as UC on TGL/RKL.


Matt

> 
> Lucas De Marchi

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795


More information about the Intel-gfx mailing list