[Intel-gfx] [PATCH 3/5] drm/i915/display: Wait at least 2 frames before selective update

[Gwan-gyeong Mun]

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>

On 9/10/21 2:07 AM, José Roberto de Souza wrote:
> BSpec states that the minimum number of frames before selective update
> is 2, so making sure this minimum limit is fulfilled.
> 
> BSpec: 50422
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 92c0b2159559f..1a3effa3ce709 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -510,7 +510,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>   	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)
>   		val |= EDP_Y_COORDINATE_ENABLE;
>   
> -	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);
> +	val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2));
>   	val |= intel_psr2_get_tp_time(intel_dp);
>   
>   	/* Wa_22012278275:adl-p */
>