[Intel-gfx] [v2] drm/i915: Update memory bandwidth parameters

[Matt Roper]

On Tue, Sep 14, 2021 at 03:07:44PM -0700, Radhakrishna Sripada wrote:
> Earlier while calculating derated bw we would use 90% of the calculated
> bw. Starting ADL-P we use a non standard derating. Updating the formulae
> to reflect the same.
> 
> Bspec: 64631
> 
> v2: Use the new derating value only for ADL-P(MattR)
> 
> Fixes: 4d32fe2f14a7 ("drm/i915/adl_p: Update memory bandwidth parameters")
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 19 ++++++++++++++++---
>  1 file changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index e91e0e0191fb..4b94256d7319 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -222,31 +222,42 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  
>  struct intel_sa_info {
>  	u16 displayrtids;
> -	u8 deburst, deprogbwlimit;
> +	u8 deburst, deprogbwlimit, derating;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
>  	.deburst = 8,
>  	.deprogbwlimit = 25, /* GB/s */
>  	.displayrtids = 128,
> +	.derating = 10,
>  };
>  
>  static const struct intel_sa_info tgl_sa_info = {
>  	.deburst = 16,
>  	.deprogbwlimit = 34, /* GB/s */
>  	.displayrtids = 256,
> +	.derating = 10,
>  };
>  
>  static const struct intel_sa_info rkl_sa_info = {
>  	.deburst = 16,
>  	.deprogbwlimit = 20, /* GB/s */
>  	.displayrtids = 128,
> +	.derating = 10,
>  };
>  
>  static const struct intel_sa_info adls_sa_info = {
>  	.deburst = 16,
>  	.deprogbwlimit = 38, /* GB/s */
>  	.displayrtids = 256,
> +	.derating = 10,
> +};
> +
> +static const struct intel_sa_info adlp_sa_info = {
> +	.deburst = 16,
> +	.deprogbwlimit = 38, /* GB/s */
> +	.displayrtids = 256,
> +	.derating = 20,
>  };
>  
>  static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
> @@ -302,7 +313,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
>  			bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
>  
>  			bi->deratedbw[j] = min(maxdebw,
> -					       bw * 9 / 10); /* 90% */
> +					       bw * (100 - sa->derating) / 100);
>  
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
> @@ -400,7 +411,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  
>  	if (IS_DG2(dev_priv))
>  		dg2_get_bw_info(dev_priv);
> -	else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
> +	else if (IS_ALDERLAKE_P(dev_priv))
> +		icl_get_bw_info(dev_priv, &adlp_sa_info);
> +	else if (IS_ALDERLAKE_S(dev_priv))
>  		icl_get_bw_info(dev_priv, &adls_sa_info);
>  	else if (IS_ROCKETLAKE(dev_priv))
>  		icl_get_bw_info(dev_priv, &rkl_sa_info);
> -- 
> 2.20.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795