[Intel-gfx] [PATCH v9 03/17] drm/i915/pxp: define PXP device flag and kconfig

[Rodrigo Vivi]

On Wed, Sep 15, 2021 at 04:29:50PM +0300, Jani Nikula wrote:
> On Fri, 10 Sep 2021, Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com> wrote:
> > Ahead of the PXP implementation, define the relevant define flag and
> > kconfig option.
> >
> > v2: flip kconfig default to N. Some machines have IFWIs that do not
> > support PXP, so we need it to be an opt-in until we add support to query
> > the caps from the mei device.
> >
> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > ---
> >  drivers/gpu/drm/i915/Kconfig             | 11 +++++++++++
> >  drivers/gpu/drm/i915/i915_drv.h          |  3 +++
> >  drivers/gpu/drm/i915/intel_device_info.h |  1 +
> >  3 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> > index f960f5d7664e..5987c3d5d9fb 100644
> > --- a/drivers/gpu/drm/i915/Kconfig
> > +++ b/drivers/gpu/drm/i915/Kconfig
> > @@ -131,6 +131,17 @@ config DRM_I915_GVT_KVMGT
> >  	  Choose this option if you want to enable KVMGT support for
> >  	  Intel GVT-g.
> >  
> > +config DRM_I915_PXP
> > +	bool "Enable Intel PXP support for Intel Gen12+ platform"
> > +	depends on DRM_I915
> > +	depends on INTEL_MEI && INTEL_MEI_PXP
> > +	default n
> > +	help
> > +	  PXP (Protected Xe Path) is an i915 component, available on GEN12+
> 
> Is GEN12+ something we still want to use in help texts?

Good catch. The + might create some confusion.
We need to change this to something like gen12 and newer,
or something like that...

> 
> BR,
> Jani.
> 
> > +	  GPUs, that helps to establish the hardware protected session and
> > +	  manage the status of the alive software session, as well as its life
> > +	  cycle.
> > +
> >  menu "drm/i915 Debugging"
> >  depends on DRM_I915
> >  depends on EXPERT
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 37c1ca266bcd..447a248f14aa 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1678,6 +1678,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >  
> >  #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
> >  
> > +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
> > +			   INTEL_INFO(dev_priv)->has_pxp) && \
> > +			   VDBOX_MASK(&dev_priv->gt)
> >  
> >  #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index d328bb95c49b..8e6f48d1eb7b 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -133,6 +133,7 @@ enum intel_ppgtt_type {
> >  	func(has_logical_ring_elsq); \
> >  	func(has_mslices); \
> >  	func(has_pooled_eu); \
> > +	func(has_pxp); \
> >  	func(has_rc6); \
> >  	func(has_rc6p); \
> >  	func(has_rps); \
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center