[Intel-gfx] [PATCH v2 0/4] drm/i915/fbc: Rework CFB stride/size calculations

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

The way we calculate the CFB stride/size is kind of a mess, and
I'm not sure if we're even allocating enough stolen memory always.
Let's make it all more straightforward, and add some new related
workarounds as well.

Some of the earlier patches already got merged, and for these
leftovers I respun the min cfb stride calcualtion a bit to be
more explicit. Mainly hoping that I can still figure out what
it's doing after a few years have passed.

Ville Syrjälä (4):
  drm/i915/fbc: Rework cfb stride/size calculations
  drm/i915/fbc: Align FBC segments to 512B on glk+
  drm/i915/fbc: Implement Wa_16011863758 for icl+
  drm/i915/fbc: Allow higher compression limits on FBC1

 drivers/gpu/drm/i915/display/intel_fbc.c | 200 +++++++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h          |   4 +-
 drivers/gpu/drm/i915/i915_reg.h          |   4 +
 3 files changed, 139 insertions(+), 69 deletions(-)

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2.32.0