[Intel-gfx] [PATCH 1/2] drm/i915/display/psr: Unset enable_psr2_sel_fetch if other checks in intel_psr2_config_valid() fails

[Hogander, Jouni]

On Tue, 2022-04-12 at 13:55 -0700, José Roberto de Souza wrote:
> If any of the PSR2 checks after intel_psr2_sel_fetch_config_valid()
> fails, enable_psr2_sel_fetch will be kept enabled causing problems
> in the functions that only checks for it and not for has_psr2.
> 
> So here moving the check that do not depend on enable_psr2_sel_fetch
> and for the remaning ones jumping to a section that unset
> enable_psr2_sel_fetch in case of failure to support PSR2.

Reviewed-by: Jouni Högander <jouni.hogander at intel.com>

> 
> Fixes: 6e43e276b8c9 ("drm/i915: Initial implementation of PSR2
> selective fetch")
> Cc: Jouni Högander <jouni.hogander at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 38 +++++++++++++---------
> --
>  1 file changed, 21 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5a55010a9b2f7..8ec7c161284be 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -891,6 +891,20 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  		return false;
>  	}
>  
> +	/* Wa_16011303918:adl-p */
> +	if (crtc_state->vrr.enable &&
> +	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR2 not enabled, not compatible with HW
> stepping + VRR\n");
> +		return false;
> +	}
> +
> +	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp,
> crtc_state)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "PSR2 not enabled, PSR2 SDP indication do
> not fit in hblank\n");
> +		return false;
> +	}
> +
>  	if (HAS_PSR2_SEL_FETCH(dev_priv)) {
>  		if (!intel_psr2_sel_fetch_config_valid(intel_dp,
> crtc_state) &&
>  		    !HAS_PSR_HW_TRACKING(dev_priv)) {
> @@ -904,12 +918,12 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  	if (!crtc_state->enable_psr2_sel_fetch &&
>  	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not
> supported this Display stepping\n");
> -		return false;
> +		goto unsupported;
>  	}
>  
>  	if (!psr2_granularity_check(intel_dp, crtc_state)) {
>  		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU
> granularity not compatible\n");
> -		return false;
> +		goto unsupported;
>  	}
>  
>  	if (!crtc_state->enable_psr2_sel_fetch &&
> @@ -918,25 +932,15 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
>  			    "PSR2 not enabled, resolution %dx%d > max
> supported %dx%d\n",
>  			    crtc_hdisplay, crtc_vdisplay,
>  			    psr_max_h, psr_max_v);
> -		return false;
> -	}
> -
> -	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp,
> crtc_state)) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "PSR2 not enabled, PSR2 SDP indication do
> not fit in hblank\n");
> -		return false;
> -	}
> -
> -	/* Wa_16011303918:adl-p */
> -	if (crtc_state->vrr.enable &&
> -	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "PSR2 not enabled, not compatible with HW
> stepping + VRR\n");
> -		return false;
> +		goto unsupported;
>  	}
>  
>  	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
>  	return true;
> +
> +unsupported:
> +	crtc_state->enable_psr2_sel_fetch = false;
> +	return false;
>  }
>  
>  void intel_psr_compute_config(struct intel_dp *intel_dp,